lh28f016sc-l Sharp Microelectronics of the Americas, lh28f016sc-l Datasheet - Page 15

• Manufacturer Part Number: lh28f016sc-l
• Description: M-bit Smartvoltage Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when V
V
bit contents are protected against alteration.
A successful set block lock-bit operation requires
that the master lock-bit be cleared or, if the master
lock-bit is set, that RP# = V
with the master lock-bit set and RP# = V
and SR.4 will be set to "1" and the operation will
fail. Set block lock-bit operations while V
V
attempted. A successful set master lock-bit
operation requires that RP# = V
with RP# = V
and the operation will fail. Set master lock-bit
operations with V
results and should not be attempted.
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and V
summary of hardware and software write protection
options.
Clear block lock-bits operation is executed by a
two-cycle command sequence. A clear block lock-
bits setup is first written. After the command is
PPH1/2/3
HH
produce spurious results and should not be
HH
. In the absence of this high voltage, lock-
on the RP# pin. See Table 5 for a
IH
, SR.1 and SR.4 will be set to "1"
IH
< RP# < V
CC
= V
HH
CC2/3/4
HH
HH
. If it is attempted
. If it is attempted
produce spurious
and V
IH
< RP# <
IH
, SR.1
PP
=
- 15 -
written, the device automatically outputs status
register data when read (see Fig. 8). The CPU can
detect completion of the clear block lock-bits event
by analyzing the RY/BY# pin output or status
register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-
Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable
clear block lock-bits operation can only occur when
V
lock-bits operation is attempted while V
SR.3 and SR.5 will be set to "1". In the absence of
this high voltage, the block lock-bit contents are
protected against alteration. A successful clear
block lock-bits operation requires that the master
lock-bit is not set or, if the master lock-bit is set,
that RP# = V
lock-bit set and RP# = V
set to "1" and the operation will fail. A clear block
lock-bits operation with V
spurious results and should not be attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
CC
PP
= V
or V
CC2/3/4
CC
transition out of valid range or RP#
HH
and V
. If it is attempted with the master
PP
= V
LH28F016SC-L/SCH-L
IH
IH
, SR.1 and SR.5 will be
PPH1/2/3
< RP# < V
. If a clear block
PP
HH
≤ V
produce
PPLK
,