lh28f016sc-l Sharp Microelectronics of the Americas, lh28f016sc-l Datasheet
lh28f016sc-l
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lh28f016sc-l Summary of contents
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... For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F016SC-L/SCH-L offer three levels of protection : absolute protection with Vpp at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs ...
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... (TSOP040-P-1020) NOTE : Reverse bend available on request. 48-BALL CSP 44-PIN SOP [LH28F016SC RY/BY ...
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... BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER DQ - OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 32 64 k-BYTE BLOCKS - 3 - LH28F016SC-L/SCH-L I LOGIC CE# WE# COMMAND USER INTERFACE OE# RP# RY/BY# WRITE V STATE PP PROGRAM/ERASE MACHINE VOLTAGE SWITCH V CC GND ...
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... HH < RP# < V produce spurious results and should not be attempted. HH (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results PP to the new voltage. Do not float any power pins. With LH28F016SC-L/SCH-L enables setting of the HH ≤ memory PP PPLK down to GND and then CC ≤ V ...
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... To take advantage of SmartVoltage technology, allow V connection to 3 1.2 Product Overview The LH28F016SC-L/SCH-L are high-performance 16 M-bit SmartVoltage flash memories organized as 2 M-byte of 8 bits. The 2 M-byte of data is arranged in thirty-two 64 k-byte blocks which are individually erasable, lockable, and unlockable in- system ...
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... The access time voltage range of 4.75 to 5.25 V over the temperature range +70°C (LH28F016SC-L)/ –40 to +85°C (LH28F016SCH-L). At 4 the access time is 100 ns or 120 ns. At lower CC ...
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... Block 010000 00FFFF 64 k-Byte Block 000000 Fig. 1 Memory Map 2 PRINCIPLES OF OPERATION The LH28F016SC-L/SCH-L SmartVoltage flash 31 memories include an on-chip WSM to manage 30 block erase, byte write, and lock-bit configuration 29 functions. It allows for : 100% TTL-level control 28 inputs, fixed power supplies during block erasure, ...
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... During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may LH28F016SC-L/SCH-L ) control and when active drives the and RP# must Fig ...
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... Fig. 2 Device Identifier Code Memory Map - 9 - LH28F016SC-L/SCH-L Reserved for Future Implementation Block 31 Lock Configuration Code Reserved for Future Implementation Block 31 (Blocks 2 through 30) Reserved for Future Implementation Block 1 Lock Configuration Code Reserved for ...
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... V V PPH1/2/3 lock-bit configuration with V voltages. V produce spurious results and should not be PPH1/2/3 HH attempted. 7. Refer to Table 3 for valid D 8. Don't use the timing both OE# and WE# are LH28F016SC-L/SCH-L voltage ≤ read operations PP PPLK on V enables PPH1/2/3 PP ADDRESS V DQ RY/BY# ...
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... Clear Block Lock-Bits command can be done while RP Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. to enable LH28F016SC-L/SCH-L (NOTE 9) SECOND BUS CYCLE (NOTE 3) (NOTE 1) (NOTE 2) Data Oper ...
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... FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written LH28F016SC-L/SCH-L voltage. RP voltage. RP# can PP ...
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... At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte - 13 - LH28F016SC-L/SCH the absence of this PP PPH1/2/3 , status register bits SR.3 and SR.4 will ...
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... Fig. 7). The CPU can detect the completion of the set lock- bit event by analyzing the RY/BY# pin output or status register bit SR. LH28F016SC-L/SCH-L must remain at PP (the same V level used for byte write) PP ...
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... active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared LH28F016SC-L/SCH-L and clear block PP PPH1/2/3 ≤ PPLK ...
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... Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register LH28F016SC-L/SCH-L EFFECT BWSS DPS " ...
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... Command Sequence SR. Error 0 1 Block Erase SR.5 = Error 0 Block Erase Successful Fig. 3 Automated Block Erase Flowchart LH28F016SC-L/SCH-L BUS COMMAND COMMENTS OPERATION Data = 20H Write Erase Setup Addr = Within Block to be Erased Erase Data = D0H Write Confirm Addr = Within Block to be Erased ...
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... SR.1 = Device Protect Error 0 1 SR.4 = Byte Write Error 0 Byte Write Successful Fig. 4 Automated Byte Write Flowchart LH28F016SC-L/SCH-L BUS COMMAND COMMENTS OPERATION Setup Data = 40H Write Byte Write Addr = Location to be Written Data = Data to be Written Write Byte Write Addr = Location to be Written ...
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... Fig. 5 Block Erase Suspend/Resume Flowchart BUS COMMAND OPERATION Erase Write Suspend Read Standby Standby Erase Write Resume Read - 19 - LH28F016SC-L/SCH-L COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR WSM Ready 0 = WSM Busy Check SR Block Erase Suspended 0 = Block Erase Completed Data = D0H Addr = X ...
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... Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Byte Write Resumed Array Data Fig. 6 Byte Write Suspend/Resume Flowchart LH28F016SC-L/SCH-L BUS COMMAND COMMENTS OPERATION Byte Write Data = B0H Write Suspend Addr = X Status Register Data Read Addr = X Check SR ...
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... Both 1 = Command Sequence Error Check SR.4 Standby 1 = Set Lock-Bit Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery LH28F016SC-L/SCH-L ...
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... Device Protect Error 0 1 Command Sequence SR. Error 0 1 Clear Block Lock-Bits SR.5 = Error 0 Clear Block Lock-Bits Successful Fig. 8 Clear Block Lock-Bits Flowchart LH28F016SC-L/SCH-L BUS COMMAND COMMENTS OPERATION Clear Block Data = 60H Write Lock-Bits Addr = X Setup Clear Block Data = D0H Write Lock-Bits ...
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... Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the System command sequence must be repeated after normal - 23 - LH28F016SC-L/SCH power supply PP CC supply traces and ...
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... RP# is first raised to V 6.2.4 through 6.2.6 "AC CHARACTERISTICS - READ-ONLY and WRITE OPERATIONS" and Fig. 13, Fig. 14 and Fig. 15 for more information. when V is LKO PP will inhibit LH28F016SC-L/SCH-L standby or sleep modes and t wake-up cycles PHQV PHWL . See Section IH ...
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... ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature • LH28F016SC-L During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F016SCH-L During Read, Block Erase, Byte Write and Lock-Bit Configuration .... –40 to +85°C Temperature under Bias ............. –40 to +85°C Storage Temperature ........................ – ...
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... TEST POINTS = 5.0±0.25 V (High Speed Testing Configuration) CC 2.0 TEST POINTS 0.8 (2 for a Logic "1" and V OH TTL OL (0 Output timing ends at V TTL 5.0±0.5 V (Standard Testing Configuration LH28F016SC-L/SCH-L UNIT CONDITION 0 0.0 V OUT 1.35 OUTPUT = 2 1.5 OUTPUT = 3.3±0.3 V and CC 2 ...
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... UNDER TEST Includes Jig L Capacitance Fig. 12 Transient Equivalent Testing Load Circuit Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, 2 (NOTE 5.0±0. 5.0±0 NOTE : 1. Applied to high-speed products, LH28F016SC-L95 and LH28F016SCH-L95. OUT - 27 - LH28F016SC-L/SCH-L C (pF 100 ...
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... LH28F016SC-L/SCH-L = 5.0±0.5 V TEST CC UNIT CONDITIONS Max ±1 µ GND Max ±10 µ GND OUT CC CMOS Inputs ...
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... V V and should not be attempted. HH (min.), between 9. RP# connection PPH1 (max.) maximum cumulative period of 80 hours. PPH2 (max.). to CCR LH28F016SC-L/SCH-L = 5.0±0.5 V TEST CC UNIT CONDITIONS MIN. MAX. – 0.5 0 2 Min ...
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... CE# without impact LH28F016SC-L/SCH-L (NOTE 1) LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 170 150 170 150 170 600 600 LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 150 120 150 120 150 600 600 ELQV ns ns ...
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... See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing after the falling Load Circuit" (Standard Configuration) for testing GLQV . characteristics LH28F016SC-L/SCH-L (NOTE 1) (NOTE 5) (NOTE 5) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. MAX. MIN. MAX. 100 120 100 120 100 120 ...
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... V IH WE# ( High Z DATA (D/Q) ( RP# ( Fig Waveform for Read Operations Device Data Valid Address Selection Address Stable t AVAV t ELQV t GLQV t GLQX t ELQX Valid Output t AVQV t PHQV - 32 - LH28F016SC-L/SCH-L t EHQZ t GHQZ t OH High Z ...
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... LH28F016SC-L/SCH-L LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 170 ns 1 µ LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 150 ns 1 µ 100 ns 100 100 ...
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... Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 11 "Transient Input/Output Reference for block erase, Waveform" and Fig. 12 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F016SC-L/SCH-L (NOTE 1) (NOTE 6) (NOTE 6) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. MAX. MIN. MAX. 100 120 ...
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... Write Read Array command. Fig Waveform for WE#-Controlled Write Operations (NOTE 3) (NOTE AVAV AVWH WHAX t WHEH t WHGL t t WHWL WHQV1/2/3/4 t WLWH t DVWH t WHDX WHRL t PHHWH t VPWH - 35 - LH28F016SC-L/SCH-L (NOTE 5) (NOTE 6) Valid D IN SRD t QVPH t QVVL ...
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... LH28F016SC-L/SCH-L LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. MAX. 170 ns 1 µ LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. MAX. 150 ns 1 µ 100 ns 100 100 ...
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... Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 11 "Transient Input/Output Reference for block erase, Waveform" and Fig. 12 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F016SC-L/SCH-L (NOTE 1) (NOTE 6) (NOTE 6) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. MAX. MIN. MAX. 100 120 ...
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... Read status register data. 6. Write Read Array command. Fig Waveform for CE#-Controlled Write Operations (NOTE 3) (NOTE AVEH EHAX t EHWH t EHGL t t EHEL EHQV1/2/3/4 t ELEH t DVEH t EHDX EHRL t PHHEH t VPEH - 38 - LH28F016SC-L/SCH-L (NOTE 5) (NOTE 6) Valid D IN SRD t QVPH t QVVL ...
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... A reset time RP# going high until outputs are valid. 4. When the device power-up, holding RP#-low minimum 100 ns is required after V range and also has been in stable there LH28F016SC-L/SCH 3.3±0 5.0±0 MIN. MAX. MIN. MAX. ...
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... C ˚ NOTE MIN. TYP. 2 6.5 2 0.4 2 0.9 2 9.5 2 0.9 3. These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested LH28F016SC-L/SCH-L (NOTE 5.0±0 12.0±0 (NOTE 1) (NOTE 1) MAX. MIN. TYP. MAX. 9.3 TBD 6.7 7.6 TBD 0.5 TBD 0.4 0.5 TBD 1 ...
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... V), 100 ns (5.0 0.5 V), 120 ns (3.3 0.3 V), 150 ns (2 120 ns (5.0 0.5 V), 150 ns (3.3 0.3 V), 170 ns (2.7 to 3.6 V) Package T = 40-pin TSOP (I) (TSOP040-P-1020) Normal bend R = 40-pin TSOP (I) (TSOP040-P-1020) Reverse bend N = 44-pin SOP (SOP044-P-0600) [LH28F016SC- 48-ball CSP (FBGA048-P-0810) VALID OPERATIONAL COMBINATIONS = 2 3.3±0 ...
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TSOP (TSOP040-P-1020 0.3 20.0 0.2 18.4 0.3 19.0 PACKAGING Package base plane ...
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SOP (SOP044-P-0600 0.4 0 0.1 0.15 M 1.27 TYP 0.2 28.2 PACKAGING 0.15 0.05 Package base plane ...
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CSP (FBGA048-P-0810 0.1 S 3.0 0.8 0 0.1 S TYP. 0.4 + 0.2 10 TYP. TYP. TYP 0.03 0. PACKAGING Land ...