z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 55

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Zilog
Expanded Register Bank F
DS97TAD0300
PCON (FH) 00H
P4D (FH) 02H
Note: Reset condition is 11111110
P5D (FH) 04H
D7 D6 D5
P4M (FH) 03H
D7 D6 D5
D7
D7 D6 D5 D4
Figure 56. Port Configuration Register (PCON)
D6 D5 D4 D3
Figure 59. Port 5 Data Register (PCON)
Figure 58. Port 4 Mode Register
Figure 57. Port 4 Data Register
D4 D3 D2
D4 D3 D2 D1
D3 D2 D1 D0
(F) 00H [Write Only]
(F) 04H [Read/Write]
(F) 02H [Write Only]
(F) 03H [Write Only]
D2 D1 D0
D1 D0
D0
P40-P47 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
Data
Returns "FF" Upon Read
R Always "1"
W 0 P34,P37
R Always "1"
W No effect
Data
1 P34,P37
Standard output
Comparator output
P R E L I M I N A R Y
P5M (FH) 05H
* Default setting after Reset
* Default setting after Reset
D7 D6 D5
P45CON (FH) 06H
SMR (FH) 0BH
*
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
† Reset After Stop-Mode Recovery
Default Setting After Reset
Figure 61. Port 4 and 5 Configuration Register
Figure 62. Stop-Mode Recovery Register
Figure 60. Port 5 Mode Register (PCON)
D5 D4 D3
D4 D3 D2 D1
(F) 07H [Read/Write]
(F) 05H [Write Only]
(F) 06H [Write Only]
D2 D1
D0
D0
Low-Cost DTAD Controller
W 000 POR only*
R
W 0 Stop delay on*
R Always "1"
W 0 Low Stop Recovery Level*
R Always "1"
W No effect
R 0 POR*
W 00 SCLK/TCLK Not Divide by 16†
R Always "1"
1 Stop-Mode Recovery
01 SCLK/TCLK Not Divide by 16
10 SCLK/TCLK Divide by 16
1 1 SCLK/TCLK Divide by 16
1 Stop delay off
1 High Stop Recovery Level
Always "1"
001 No effect
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Z89135/136 (ROMless)
P50-P57 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input*
Port 4 Configuration Bit
Reserved
Port 5 Configuration Bit
Reserved
0 Open Drain *
1 Push-pull Active
0 Open Drain *
1 Push-pull Active
Returns "FF" Upon Read
1-55
1