z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 51

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Zilog
PULSE WIDTH MODULATOR (PWM)
The PWM supports four different sampling rates (4, 10, 16,
and 64 kHz), according to the settings of Bit 8, 9, 10 of the
ACR. The output of PWM can be assigned to logic 1 only
during the active region (which is 4/5 of the output signal
period). The output will be at logic 0 for the rest of the time.
An exception occurs in 10 kHz PWM, where the active re-
gion covers the whole output signal period (Figure 37). The
active region is divided into 1024 time slots. In each of
these time slots, the output can be set to logic 1 or logic 0.
In order to increase the effective sampling rate, the PWM
employs a special technique of distributing the “logic 1” pe-
riod over the active region.
The 10-bit PWM data is divided into two parts: the upper 5
bits (High_Val) and the lower 5 bits (Low_Val). The 1024
time slots in the active region are divided into 32 equal
groups, with 32 time slots in each group. The first slot of
each of the 32 groups represents Low_Val, while High_Val
DS97TAD0300
16 s
16 s
62.5 s
62.5 s
100 s
100 s
Figure 38. PWM Waveform of the Active Region
(shaded area shows the active region)
250 s
250 s
Figure 37. PWM Waveform
(for a 6-bit PWM data)
P R E L I M I N A R Y
is represented by the remaining 31 time slots in each
group.
For example, a value of %13a is loaded into PWM data
register EXT 5:
26 out of 32 groups will then have their first slots set to log-
ic 1. The remaining slots in each group have 9 time slots
set to logic 1.
For 10 kHz PWM, the effective output frequency is 10K x
32 = 320 kHz. Figure 38 illustrates the waveform by using
a 6-bit PWM data (3-bit High_Val and 3-bit Low_Val).
%13a = 01 0011 1010B = 314
High_Val = 01001B = 9
Low_Val = 11010B = 26
Low-Cost DTAD Controller
Z89135/136 (ROMless)
4 kHz
10 kHz
16 kHz
64 kHz
4 kHz
10 kHz
16 kHz
64 kHz
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