z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 21

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Zilog
Port 0. (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS-
compatible port. These eight I/O lines are configured un-
der software control as a nibble I/O port, or as an address
port for interfacing external memory. The input buffers are
Schmitt-triggered and the output drivers are push-pull.
Port 0 is placed under handshake control. In this configu-
ration, Port 3, lines P32 and P35 are used as the hand-
shake control /DAV0 and RDY0. Handshake signal direc-
tion is dictated by the I/O direction to Port 0 of the upper
nibble P07-P04. The lower nibble must have the same di-
rection as the upper nibble.
The Auto Latch on Port 0 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply cur-
rent flow in the input buffer.
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
DS97TAD0300
OEN
Out
In
1.5
Z89135/136
MCU
Figure 10. Port 0 Configuration
2.3V Hysteresis
P R E L I M I N A R Y
R = 500 K
4
4
ble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of
Port 0 can be programmed independently as I/O while the
lower nibble is used for addressing. If one or both nibbles
are needed for I/O operation, they are configured by writ-
ing to the Port 0 mode register.
In ROMless mode, after a hardware reset, Port 0 is config-
ured as address lines A15-A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
input after reset.)
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control sig-
nals /AS, /DS and R//W (Figure 10).
Port 0
(I/O or A15 - A8)
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
Auto Latch
Low-Cost DTAD Controller
Z89135/136 (ROMless)
PAD
1-21
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