z89136 ZiLOG Semiconductor, z89136 Datasheet
z89136
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z89136 Summary of contents
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... DSP or Z8 pro- ® MCU with 24 grams to be directed by events in each other’s domain. The Z89136 is the ROMless version of the Z89135. The DSP is not ROMless. The DSP's program memory is al- ways the internal ROM ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller GENERAL DESCRIPTION (Continued) P00 P01 P02 Address P03 or I/O Port 0 (Nibble P04 Programmable) P05 P06 P07 P10 P11 P12 Address/Data P13 or I/O Port 1 P14 (Byte Programmable) P15 P16 P17 P20 P21 ...
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Zilog Z8 Core Processor The Z8 is Zilog’s 8-bit MCU core with an Expanded Regis- ter File to allow access to register-mapped peripheral and ® I/O circuits. The Z8 MCU offers a flexible I/O scheme, an efficient register and address ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller 9 8 XTAL2 10 XTAL1 11 P22 12 P56 13 P23 14 P55 15 P54 16 GND 17 P17 18 P05 19 P24 20 P16 21 P25 22 P15 23 P26 24 P27 25 N/C ...
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Zilog Table 1. Z89135 68-Pin Plastic Leaded Chip Carrier, Pin Identification Pin # Symbol Function 1 RMLS ROMless 2 V Power Supply DD 3 P04 Port 0, Bit 4 4 P50 Port 5, Bit 0 5 P57 Port 5, Bit ...
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... P17 18 P05 19 P24 20 P16 21 P25 22 P15 23 P26 24 P27 25 SCLK Figure 3. Z89136 68-Pin PLCC Pin Assignments 1 Z89136 Zilog 60 VREF+ 59 ANIN 58 VREF- ...
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... Port 3, Bit 3 30 P34 Port 3, Bit Power Supply DD 32 P35 Port 3, Bit 5 33 P14 Port 1, Bit 4 34 DSP1 DSP User Output 1 DS97TAD0300 Table 2. Z89136 68-Pin Plastic Leaded Chip Carrier, Direction Pin # Symbol Function 35 DSP0 36 P36 37 P13 Input/Output 38 P37 Input/Output 39 P40 Input/Output 40 P12 ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller A/D CONVERTER (ADC) Figure 4 shows the input circuit of the ADC. When conver- sion starts, the analog input voltage from the input is con- nected to the MSB and LSB flash converter inputs as ...
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Zilog STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 5). CAPACITANCE GND = 0V, ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller DC ELECTRICAL CHARACTERISTICS Sym Parameter V Max Input Voltage MAX V Clock Input High Voltage CH V Clock Input Low Voltage CL V Input High Voltage IH V Input Low Voltage IL V Output High ...
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Zilog DC ELECTRICAL CHARACTERISTICS Z89165 A/D Converter Sym Parameter I Input Leakage Analog Input IL I Input Leakage Analog Input IH I Input Current VREFH V Input Current I REFL IVEFL Input Current I Input Current VREFL DS97TAD0300 T = ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller DC ELECTRICAL CHARACTERISTICS 21 Other Non-Regular I/O Sym Parameter I Input Current ROMless Pin IRH I Input Current ROMless Pin IR1 I Input Current ROMless Pin IR During Reset Active I Input Current XTAL2 pin ...
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Zilog AC CHARACTERISTIC External I/O or Memory Read and Write Timing Diagram R//W 12 Port 0, /DM 19 Port 1 1 /AS 4 /DS (Read) Port1 /DS (Write) Figure 6. External I/O or Memory Read/Write Timing DS97TAD0300 ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table No Symbol Parameter 1 TdA(AS) Address Valid to /AS Rise Delay 2 TdAS(A) /AS Rise to Address Float Delay 3 TdAS(DR) /AS Rise to ...
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Zilog AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram Clock TIN 4 IRQN 8 Clock Setup Stop Mode Recovery Source DS97TAD0300 Figure 7. Additional Timing ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller AC ELECTRICAL CHARACTERISTICS Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH ...
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Zilog AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In 1 /DAV (Input) RDY (Output) Data Out /DAV (Output) RDY (Input) DS97TAD0300 Data In Valid 2 3 Delayed DAV 4 Figure 8. Input Handshake Timing Data Out Valid ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller AC ELECTRICAL CHARACTERISTICS (Continued) Handshake Timing Table No Symbol Parameter 1 TsDI(DAV) Data In Setup Time 2 ThDI(DAV) RDY to Data Hold Time 3 TwDAV Data Available Width 4 TdDAVI(RDY) DAV Fall to RDY Fall ...
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Zilog AC ELECTRICAL CHARACTERISTICS A/D Electrical Characteristics – 5.0V 0.25V A CC Parameter Resolution Integral non-linearity Differential non-linearity Zero Error Power Dissipation Clock Frequency Clock Pulse Width Analog Input Voltage ...
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... EXT4). This bit has no special significance and may be used to output data by writing to bit 7 of the ACR. SCLK. System Clock (output). SCLK outputs the system clock. This pin is available on the Z89136. /SYNC. Synchronize (output). This signal indicates the last clock cycle of the current executing Z8 instruction. This pin is only available on the Z89136 ...
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Zilog Port 0. (P07-P00). Port 8-bit, bidirectional, CMOS- compatible port. These eight I/O lines are configured un- der software control as a nibble I/O port address port for interfacing external memory. The input buffers ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller PIN FUCTIONS (Continued) Port 1. (P17-P10). Port 8-bit, bidirectional, CMOS- compatible port (Figure11). It has multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines are programmed as inputs or outputs, ...
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Zilog Port 2. (P27-P20). Port 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines are configured under software control as an input or output, independent- ly. Port 2 is always available for I/O operation. The input ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller PIN FUCTIONS (Continued) Port 3. (P37-P31). Port 7-bit, CMOS-compatible port with three fixed inputs (P33-P31) and four fixed outputs (P37-P34 configured under software control for in- put/output, counter/timers, interrupt, and ...
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Zilog P31 (AN1) P32 (AN2) P33 (REF) From Stop Mode Recovery Source DS97TAD0300 Port 3 Z89135/136 (I/O or Control) MCU R247 = P3M D1 DIG Figure 13. Port 3 Configuration ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller PIN FUCTIONS (Continued) Port 4. (P47-P40). Port 8-bit, bidirectional, CMOS- compatible I/O port (Figure 14). These eight I/O lines are configured under software control as an input or output, in- dependently. Port ...
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Zilog Port 5. (P57-P50). Port 8-bit, bidirectional, CMOS- compatible I/O port (Figure 15). These eight I/O lines are configured under software control as an input or output, in- dependently. Port 5 is always available for I/O operation. ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION The Z8 CCP™ core incorporates special functions to en- hance the Z8’s application in industrial, scientific research and advanced technologies applications. Reset. The device is reset in one of the following condi- tions: ...
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Zilog ROM Protect. The internal program memory for the Z8 is mask programmable. A ROM protect feature pre- vents “dumping” of the ROM contents of Program Memory by inhibiting execution of LDC, LDCI, LDE, and LDEI in- ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION (Continued) Register File. The standard Z8 register file consists of four I/O port registers, 236 general-purpose registers, and 15 control and status registers (R3-R0, R239-R4, and R255- R241, respectively). The instructions access registers ...
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Zilog RAM Protect. The upper portion of the Z8’s RAM address spaces 80FH to EFH (excluding the control registers) are protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the cus- tomer when ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION (Continued) REGISTER POINTER Working Register Expanded Register Group Pointer Z8 Reg. File FFH FOH 7FH 0FH 00H Figure 20. Expanded Register File Architecture 1-32 Z8 STANDARD ...
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Zilog Global Interrupt Enable Interrupt Request Table 4. Interrupt Types, Sources, and Vectors Name Source IRQ0 /DAV0, P32, AN2 IRQ1 /DAV1, P33 IRQ2 /DAV2, P31,T , AN2 IN IRQ3 IRQ3 IRQ4 T0 IRQ5 TI DS97TAD0300 IRQ0 IRQ2 IRQ1 ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION (Continued) Interrupts. The Z8 has six different interrupts from six dif- ferent sources. The interrupts are maskable and prioritized (Figure 21). The six sources are divided as follows; three sources are claimed by ...
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Zilog Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit pro- grammable prescaler. The T1 prescaler is driven by inter- nal or external clock sources; however, the T0 prescaler is driven by the internal clock ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION (Continued) Port Configuration Register (PCON). The PCON regis- ter configures the port individually; comparator output is on Port 3. The PCON register is located in the Expanded Register File at Bank F, location ...
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Zilog Power-On Reset (POR). A timer circuit clocked by a ded- icated on-board RC oscillator is used for the Power-On Re- set (POR) timer function. The POR time allows V the oscillator circuit to stabilize before instruction execu- tion begins. ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION (Continued) Stop-Mode Recovery Register (SMR). This register se- lects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 26). All bits are Write Only, except bit 7 which is Read ...
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Zilog SCLK/TCLK divide-by-16 Select (D0 the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The pur- pose of this control is to selectively reduce device power consumption during normal processor execution (SCLK SMR ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller FUNCTIONAL DESCRIPTION (Continued) DSP Control Register (DSPCON). The DSPCON register controls various aspects of the Z8 and the DSP. It can con- figure the internal system clock (SCLK) or the Z8, RESET, Field DSPCON (F)0CH ...
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Zilog Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subse- quent executions of ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller WDT Time Select (D0,D1). Selects the WDT time period configured as shown in Table 8. Table 8. WDT Time Select Time-out Internal RC OSC min 0 ...
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Zilog DSP REGISTERS DESCRIPTION General. The DSP is a high-performance second genera- tion CMOS Digital Signal Processor with a modified Har- vard-type architecture with separate program and data ports. The design has been optimized for processing pow- er and saving ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller (B)00, (B)01 (B)02, (B)03 (B)04, (B)05 (B)06, (B)07 (B)08, (B)09 (B)0A, (B)0B (B)0C, (B)0D (B)0E, (B)0F (F)0C D7, D1 DSP-Z8 MAILBOX To receive information from the DSP, the Z8 uses eight in- coming registers which ...
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Zilog Field Outgoing [0] (B)00 Outgoing [1] (B)01 Outgoing [2] (B)02 Outgoing [3] (B)03 Outgoing [4] (B)04 Outgoing [5] (B)05 Outgoing [6] (B)06 Outgoing [7] (B)07 Field Incoming [8] (B)08 Incoming [9] (B)09 Incoming [a] (B)0A Incoming [b] (B)0B Incoming ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller DSP INTERRUPTS The DSP processor has three interrupt sources (INT2, INT1, INT0) (Figure 31). These sources have different pri- ority levels (Figure 32). The highest priority, the next lower and the lowest priority level are ...
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Zilog Table 13. Field Position DSP_IRQ2 f--------------- f--------------- DSP_IRQ1 -e-------------- -e-------------- DSP_IRQ0 --d------------- --d------------- DSP_MaskINT2 ---c------------ DSP_MaskINT1 ----b----------- DSP_MaskINT0 -----a---------- Z8_IRQ3 ------9--------- ------9--------- DSPintEnable -------8-------- DSP_IPR2 --------7------- DSP_IPR1 ---------6------ DSP_IPR0 ----------5----- Clear_IRQ2 -----------4---- -----------4---- Clear_IRQ1 ------------3--- ------------3--- Clear_IRQ0 -------------2-- -------------2-- ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller Z8_IRQ3. This bit can be read from both Z8 and DSP and can be set by DSP only. Addressing this location accesses bit D3 of the Z8 IRQ register, hence this bit is not imple- ...
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Zilog ANALOG CONTROL REGISTER (ACR) The Analog Control register is mapped to register EXT6 of the DSP (Table 15). This read/write register is accessible by the DSP only. Table 15. EXT6 Analog Control Register (ACR) Field Position MPX_DSP_INT0 f--------------- Reserved ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller DSP IRQ0. This bit defines the source of DSP IRQ0 inter- rupt. D/A_Sampling Rate. This field defines the sampling rate of the D/A output. It changes the period to Timer3 interrupt and the maximum possible ...
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Zilog PULSE WIDTH MODULATOR (PWM) The PWM supports four different sampling rates (4, 10, 16, and 64 kHz), according to the settings of Bit the ACR. The output of PWM can be assigned to logic 1 ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller A/D CONVERTER (ADC) Analog To Digital Converter The A/D converter is an 8-bit half flash converter which uses two reference resistor ladders for its upper four bits (MSBs) and lower four bits (LSBs) conversion. Two ...
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Zilog Z8 EXPANDED REGISTER FILE REGISTERS Expanded Register Bank B ( Figure 40. Outgoing Register to DSP EXT0 (High Byte) (B) 00H [Read/Write] ( ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller Z8 EXPANDED REGISTER FILE REGISTERS (Continued) ( Figure 48. Incoming Register to DSP EXT0 (High Byte) (B) 08H [Read/Write] ( ...
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Zilog Expanded Register Bank F PCON (FH) 00H Note: Reset condition is 11111110 Figure 56. Port Configuration Register (PCON) (F) 00H [Write Only] P4D (FH) 02H ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller Field DSPCON (F)0CH Z8_SCLK DSP_Reset DSP_Run Reserved IntFeedback WDTMR (FH) 0FH Default setting after RESET Note: The WDTMR Register is only accessed within 64 Z8 clock ...
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Zilog Z8 CONTROL REGISTERS Figure 64. Reserved (F0H) R241 TMR Figure 65. Timer Mode Register (F1H: Read/Write) R242 ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller Z8 CONTROL REGISTERS (Continued) R246 P2M Default Setting After Reset Figure 70. Port 2 Mode Register (F6H: Write Only) R247 P3M ...
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Zilog R250 IRQ Figure 74. Interrupt Request Register R251 IMR Figure 75. Interrupt Mask Register (FBH: Read/Write) R252 FLAGS ...
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Zilog PACKAGE INFORMATION DS97TAD0300 Figure 80. 68-Pin PLCC Package Diagram Z89135/136 (ROMless) Low-Cost DTAD Controller 1 1-60 ...
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... Z 89135 Z89135, 20.48 MHz, PLCC +55 C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix DS97TAD0300 Z89136 20 MHz Temperature +55 C Environmental C = Plastic Standard Z89135/136 (ROMless) Low-Cost DTAD Controller ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller 1- Zilog DS97TAD0300 ...
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Zilog DS97TAD0300 Z89135/136 (ROMless) Low-Cost DTAD Controller 1 1-63 ...
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Z89135/136 (ROMless) Low-Cost DTAD Controller 1- Zilog DS97TAD0300 ...
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Zilog DS97TAD0300 Z89135/136 (ROMless) Low-Cost DTAD Controller 1 1-65 ...
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Zilog DS97TAD0300 Z89135/136 (ROMless) Low-Cost DTAD Controller 1 1-66 ...