z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 39

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Zilog
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
DS97TAD0300
SMR D4 D3 D2
D4
0
0
0
0
1
1
1
1
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
SMR:432
0
VDD
D3
Table 6. Stop-Mode Recovery Source
0
0
1
1
0
0
1
1
0
P31
P32
0
D2
0
1
0
1
0
1
0
1
SMR
POR and/or external reset recovery
No effect
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
D4 D3 D2
0
0
1
1
P33
Description of Action
0
1
SMR
Operation
D4 D3 D2
1
0
Figure 27. Stop-Mode Recovery Source
P27
0
SMR
P R E L I M I N A R Y
D4 D3 D2
1
0
P20
P23
1
control) and/or HALT Mode (where TCLK sources
counter/timers and interrupt logic).
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the Stop-Mode
Recovery (Figure 27 and Table 6).
Stop-Mode Recovery Delay Select (D5). This bit, if High,
disables the 5 ms /RESET delay after Stop-Mode Recov-
ery. The default configuration of this bit is one. If the “fast”
wake-up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a high level on any one of the recovery
sources wakes the Z89165 from STOP Mode. A 0 indi-
cates low level recovery. The default is 0 on POR .
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read Only. It is used to
distinguish between cold or warm start.
SMR
D4 D3 D2
1
1
P20
P27
0
Low-Cost DTAD Controller
SMR
MUX
Z89135/136 (ROMless)
D4 D3 D2
1
1
1
T o P33 Data
Latch and IRQ1
T o POR
RESET
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1