z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 37

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Zilog
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (POR) timer function. The POR time allows V
the oscillator circuit to stabilize before instruction execu-
tion begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock,
RC/LC oscillators).
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-
vices are recovered by interrupts, either externally or inter-
nally generated.
DS97TAD0300
Power fail to Power OK status
Stop-Mode Recovery (if D5 of SMR=1)
WDT time-out.
P R E L I M I N A R Y
CC
and
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation. It reduces the standby current to
300
only, either by WDT time-out, POR, SMR recovery or ex-
ternal reset. This causes the processor to restart the appli-
cation program at address 000CH. In order to enter STOP
(or HALT) Mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode=FFH)
immediately before the appropriate sleep instruction, for
example:
FF
6F
FF
7F
A or less. The STOP Mode is terminated by a reset
NOP
STOP
NOP
HALT
Low-Cost DTAD Controller
;clear the pipeline
;enter STOP Mode
;clear the pipeline
;enter HALT Mode
or
Z89135/136 (ROMless)
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