isp1181 NXP Semiconductors, isp1181 Datasheet - Page 37

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isp1181

Manufacturer Part Number
isp1181
Description
Isp1181 Full-speed Universal Serial Bus Interface Device
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
Table 36:
9397 750 08938
Product data
Bit
Symbol
Reset
Access
Error Code Register: bit allocation
UNREAD
R
7
0
12.2.7 Acknowledge Setup
12.3.1 Read Endpoint Error Code
12.3 General commands
Table 35:
This command acknowledges to the host that a SETUP packet was received. The
arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands
for the control IN and OUT endpoints. The microcontroller needs to re-enable these
commands by sending an Acknowledge Setup command, see
Remark: The Acknowledge Setup command must be sent to both control endpoints
(IN and OUT).
Code (Hex): F4 — acknowledge setup
Transaction — none
This command returns the status of the last transaction of the selected endpoint, as
stored in the Error Code Register. Each new transaction overwrites the previous
status information. The bit allocation of the Error Code Register is shown in
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte
Bit
3
2
1
0
DATA01
R
6
0
Endpoint Status Image Register: bit description
Symbol
OVERWRITE
SETUPT
CPUBUF
-
reserved
R
5
0
Rev. 04 — 30 October 2001
Description
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
R
4
0
R
3
0
ERROR[3:0]
R
2
0
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
…continued
Full-speed USB interface
Section
R
1
0
ISP1181
9.5.
Table
RTOK
R
0
0
37 of 71
36.

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