isp1181 NXP Semiconductors, isp1181 Datasheet - Page 35

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 32:
9397 750 08938
Product data
Bit
Symbol
Reset
Access
Endpoint Status Register: bit allocation
EPSTAL
R
7
0
12.2.3 Stall Endpoint/Unstall Endpoint
EPFULL1
Table 33:
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status Register (see
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an
OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoint 1 to 14)
Transaction — none
Bit
7
6
5
4
3
2
1
0
R
6
0
Endpoint Status Register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
EPFULL0
R
5
0
Rev. 04 — 30 October 2001
DATA_PID
Description
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled upon reception of a SETUP token.
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the present packet
(0 = DATA PID, 1 = DATA1 PID).
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
R
4
0
WRITE
OVER
R
3
0
Table
SETUPT
32).
R
2
0
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Full-speed USB interface
CPUBUF
R
1
0
ISP1181
reserved
R
0
0
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