isp1181 NXP Semiconductors, isp1181 Datasheet - Page 27

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 15:
Table 17:
9397 750 08938
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Endpoint Configuration Register: bit allocation
Address Register: bit allocation
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
12.1.2 Write/Read Device Address
12.1.3 Write/Read Mode Register
Table 16:
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the Address Register (accessible by the micro) is not altered by the bus
reset. In response to the standard USB request Set Address the firmware must issue
a Write Device Address command, followed by sending an empty packet to the host.
The new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write/read Address Register
Transaction — write/read 1 byte
Table 18:
This command is used to access the ISP1181 Mode Register, which consists of
1 byte (bit allocation: see
The Mode Register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
EPDIR
R/W
R/W
6
0
6
0
Endpoint Configuration Register: bit description
Address Register: bit description
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Symbol
DEVEN
DEVADR[6:0]
DBLBUF
R/W
R/W
5
0
5
0
Rev. 04 — 30 October 2001
FFOISO
Table
Description
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write)
A logic 1 indicates that this endpoint has double buffering.
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
Selects the FIFO size according to
Description
A logic 1 enables the device.
This field specifies the USB device address.
R/W
R/W
4
0
4
0
18). In 16-bit bus mode the upper byte is ignored.
DEVADR[6:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
FFOSZ[3:0]
Full-speed USB interface
Table 5
R/W
R/W
1
0
1
0
ISP1181
Table
R/W
R/W
17.
0
0
0
0
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