isp1181 NXP Semiconductors, isp1181 Datasheet - Page 31

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 25:
[1]
9397 750 08938
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DMA Configuration Register: bit allocation
CNTREN
R/W
R/W
0
0
15
7
[1]
[1]
12.1.6 Write/Read DMA Configuration
SHORTP
Table 24:
This command defines the DMA configuration of ISP1181 and enables/disables DMA
transfers. The command accesses the DMA Configuration Register, which consists of
2 bytes. The bit allocation is given in
disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write/read DMA Configuration
Transaction — write/read 2 bytes
Table 26:
Bit
7, 6
5
4
3
2
1
0
Bit
15
14
13 to 8
7 to 4
R/W
R/W
0
0
14
6
[1]
[1]
EPDIX[3:0]
Interrupt Enable Register: bit description
DMA Configuration Register: bit description
Symbol
-
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
Symbol
CNTREN
SHORTP
-
EPDIX[3:0]
reserved
R/W
R/W
0
0
13
5
[1]
[1]
Rev. 04 — 30 October 2001
reserved
Description
reserved
A logic 1 enables 1 ms interrupts upon detection of Pseudo
SOF.
A logic 1 enables interrupt upon SOF detection.
A logic 1 enables interrupt upon EOT detection.
A logic 1 enables interrupt upon detection of ‘suspend’ state.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a bus reset.
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
reserved
Indicates the destination endpoint for DMA, see
R/W
R/W
0
0
12
4
[1]
[1]
Table
reserved
DMAEN
R/W
R/W
0
11
3
0
[1]
25. A bus reset will clear bit DMAEN (DMA
reserved
reserved
…continued
R/W
R/W
0
10
2
0
[1]
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Full-speed USB interface
reserved
R/W
R/W
0
0
9
1
[1]
[1]
BURSTL[1:0]
ISP1181
Table
reserved
7.
R/W
R/W
0
0
8
0
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