mc68hc05jp6pe Freescale Semiconductor, Inc, mc68hc05jp6pe Datasheet - Page 151

• Manufacturer Part Number: mc68hc05jp6pe
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.4 Core Timer Counter Register
MC68HC05JJ6/MC68HC05JP6
Freescale Semiconductor
TOF = 1/(f
MHz
488
4.2
Interrupt Period
(microseconds)
Timer Overflow
@ f
OSC
1024
MHz
2.0
OSC
(MHz)
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
2048
MHz
1.0
2
11
)
RT1 RT0
0
0
1
1
A 15-stage ripple counter driven by a divide-by-eight prescaler is the
basis of the core timer. The value of the first eight stages is readable at
any time from the read-only timer counter register as shown in
Figure
Power-on clears the entire counter chain and begins clocking the
counter. After the startup delay (16 or 4064 internal bus cycles
depending on a mask option), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or
four cycles of the internal bus. A timer overflow function at the eighth
counter stage allows a timer interrupt every 2048 oscillator clock cycles
or every 1024 internal bus cycles.
Reset:
$0009
Read:
Write:
0
1
0
1
—
Rev. 3.2
divided
= f
10-3.
Rate
RTI
Figure 10-3. Core Timer Counter Register (CTCR)
by:
2
2
2
2
Bit 7
Bit 7
OSC
15
16
17
18
0
MHz
7.80
15.6
31.2
62.4
= Unimplemented
4.2
Interrupt Period
(milliseconds)
@ f
6
6
0
Real-Time
Core Timer
OSC
(RTI)
MHz
16.4
32.8
65.5
131
2.0
(MHz)
5
5
0
MHz
32.8
65.5
131
262
1.0
4
4
0
54.6
Min
109
218
437
4.2 MHz
Max
62.4
COP = 7 to 8 RTI Periods
125
250
499
3
3
0
COP Timeout Period
(milliseconds)
General Release Specification
@ f
Min
115
229
459
918
2.0 MHz
OSC
2
2
0
(MHz)
1049
Max
131
262
524
1
1
0
1835
Min
229
459
918
1.0 MHz
Core Timer
Bit 0
Bit 0
1049
2097
Max
262
524
0
151