mc68hc05jp6pe Freescale Semiconductor, Inc, mc68hc05jp6pe Datasheet - Page 100

• Manufacturer Part Number: mc68hc05jp6pe
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Parallel Input/Output
7.5.2 Data Direction Register C
7.5.3 Port C Pulldown Devices
General Release Specification
100
The contents of the port C data direction register (DDRC) determine
whether each port C pin is an input or an output. Writing a logic one to a
DDRC bit enables the output buffer for the associated port C pin. A
DDRC bit set to a logic one also disables the pulldown device for that pin.
Writing a logic zero to a DDRC bit disables the output buffer for the
associated port C pin. A reset initializes all DDRC bits to logic zeros,
configuring all port C pins as inputs.
DDRC7–DDRC0 — Port C Data Direction Bits
All port C pins can have software programmable pulldown devices
enabled or disabled by the software pulldown inhibit mask option. When
enabled these pulldowns can sink approximately 100 A. These
pulldown devices are controlled by the write-only pulldown register A
(PDRA) shown in
(PC7:PC4) and PDICL controls the lower four pins (PC3:PC0). Clearing
the PDICH or PDICL bits in the PDRA turns on the pulldown devices if
the port C pin is an input. Reading the PDRA returns undefined results
since it is a write-only register. Reset clears the PDICH and PDICL bits,
which turns on all the port C pulldown devices.
Reset:
These read/write bits control port C data direction. Reset clears the
DDRC7–DDRC0 bits.
$0006
Read:
Write:
1 = Corresponding port C pin configured as output and pulldown
0 = Corresponding port C pin configured as input
device disabled
DDRC7
Bit 7
Figure 7-14. Data Direction Register C (DDRC)
0
Parallel Input/Output
DDRC6
Figure
6
0
DDRC5
7-3. PDICH controls the upper four pins
5
0
DDRC4
4
0
MC68HC05JJ6/MC68HC05JP6
DDRC3
3
0
DDRC2
Freescale Semiconductor
2
0
DDRC1
1
0
—
Rev. 3.2
DDRC0
Bit 0
0