ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 8

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

4.1.4
4.1.5
4.1.6
4.1.7
8
ATA6020N
ALU
I/O Bus
Instruction Set
Interrupt Structure
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele-
ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU
operations affects the carry/borrow and branch flag in the condition code register (CCR).
Figure 4-5.
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication
between the core and the on-chip peripherals take place via the I/O bus and the associated I/O
control. With the MARC4 IN and OUT instructions, the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip periph-
erals is described in the section
not accessible by the customer on the final microcontroller device, but it is used as the interface
for the MARC4 emulation (see section “Emulation”).
The MARC4 instruction set is optimized for the high level programming language qFORTH.
Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and
compact program code. The CPU has an instruction pipeline allowing the controller to prefetch
an instruction from ROM at the same time as the present instruction is being executed. The
MARC4 is a zero address machine, the instructions containing only the operation to be per-
formed and no source or destination address fields. The operations are implicitly performed on
the data placed on the stack. There are one- and two-byte instructions which are executed
within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles
(SYSCL). Most of the instructions are only one byte long and are executed in a single machine
cycle. For more information refer to the “MARC4 Programmer’s Guide”.
The MARC4 can handle interrupts with eight different priority levels. They can be generated
from the internal and external interrupt sources or by a software interrupt from the CPU itself.
Each interrupt level has a hard-wired priority and an associated vector for the service routine in
ROM (see
resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered,
but the interrupt routine only starts after the I-flag is set. All interrupts can be masked, and the
priority individually software configured by programming the appropriate control register of the
interrupting module (see section
Table 4-1 on page
SP
ALU Zero-address Operations
RAM
TOS-2
TOS-1
TOS-3
TOS-4
10). The programmer can postpone the processing of interrupts by
“Peripheral Modules” on page
“Peripheral Modules” on page
CCR
ALU
TOS
20. The I/O bus is internal and is
20).
4708D–4BMCU–09/05