ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 25

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

5.2.2.1
5.2.2.2
Table 5-3.
5.2.3
4708D–4BMCU–09/05
Auxiliary Address:’5’hex
P5DAT
P5CR
3 2 1 0
x x 1 1
x x 0 1
x x 1 0
x x 0 0
1 1 x x
0 1 x x
1 0 x x
0 0 x x
Code
Function
BP50 in input mode - interrupt disabled
BP50 in input mode - rising edge interrupt
BP50 in input mode - falling edge interrupt
BP50 in output mode - interrupt disabled
BP51 in input mode - interrupt disabled
BP51 in input mode - rising edge interrupt
BP51 in input mode - falling edge interrupt
BP51 in output mode - interrupt disabled
Bi-directional Port 4
Port 5 Data Register (P5DAT)
Port 5 Control Register (P5CR) Byte Write
Port 5 Control Register
First write cycle
Second write cycle
Bit 3
P5DAT3
P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code
The bi-directional Port 4 is both a bitwise configurable I/O port and provides the external pins for
the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the
same way as bi-directional Port 2 (see
data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI).
The I/O-pins for the SC and SD lines have an additional mode to generate an SSI-interrupt.
All four Port 4 pins can be individually switched by the P4CR-register.
shows the internal interfaces to bi-directional Port 4.
First Write Cycle
Bit 2
P5DAT2
Bit 3
P51M2
Bit 7
P53M2
Bit 2
P51M1
Bit 6
P53M1
P5DAT1
Bit 1
Second Write Cycle
3 2 1 0
x x 1 1
x x 0 1
x x 1 0
x x 0 0
1 1 x x
0 1 x x
1 0 x x
0 0 x x
Code
Bit 1
P50M2
Bit 5
P52M2
Figure 5-2 on page
Bit 0
P5DAT0
Function
BP52 in input mode – interrupt disabled
BP52 in input mode – rising edge interrupt
BP52 in input mode – falling edge interrupt
BP52 in output mode – interrupt disabled
BP53 in input mode – interrupt disabled
BP53 in input mode – rising edge interrupt
BP53 in input mode – falling edge interrupt
BP53 in output mode – interrupt disabled
Bit 0
P50M1
Bit 4
P52M1
22). Two additional multiplexes allow
Primary register address:’5’hex
Reset value: 1111b
Auxiliary register address:’5’hex
Reset value: 1111b
Reset value: 1111b
Figure 5-5 on page 26
ATA6020N
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