ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 50

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ATA6020N

Manufacturer Part Number
ATA6020N
Description
Low-current Microcontroller For Watchdog Function
Manufacturer
ATMEL Corporation
Datasheet

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5.2.7.12
50
ATA6020N
Serial Interface Control Register 2 (SIC2)
Table 5-13.
SDD controls port directional control and defines the reset function for the SRDY-flag
SIC2
MSM
SM1
SM0
SDD
• In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded
• Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous
• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop
(SRDY = 1).
8-bit mode only).
condition.
Mode
1
2
3
4
Bit 3
MSM
Modular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) - used in modulation
Serial Mode control bit 1
Serial Mode control bit 0
Serial Data Direction
SDD = 1, transmit mode - SD line used as output (transmit data). SRDY is set by a
SDD = 0, receive mode - SD line used as input (receive data). SRDY is set by a
Serial Mode Control Bits
SM1
modes for generating bit streams which are not sub–multiples of 8 bit.
1
1
0
0
Bit 2
SM1
Bit 1
SM0
SM0
receive buffer read access
1
0
1
0
transmit buffer write access
Bit 0
SDD
SSI Mode
8-bit NRZ-Data changes with the rising edge of SC
8-bit NRZ-Data changes with the falling edge of SC
9-bit two-wire MCL compatible
8-bit two-wire pseudo MCL compatible (no acknowledge)
Auxiliary register address: ’A’hex
Reset value: 1111b
4708D–4BMCU–09/05

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