ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 18

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

4.4.3
4.4.3.1
4.4.3.2
18
ATA6020N
Clock Management
Clock Management Register (CM)
System Configuration Register (SC)
The clock management register controls the system clock divider and synchronization stage.
Writing to this register triggers the synchronization cycle.
Table 4-6.
CM
NSTOP
CCS
CSS1
CSS0
SC: write
BOT
OS1
OS0
CSS1
0
1
1
0
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, an external clock source or the RC-oscillator 2 with the external
Core Speed Select 1
Core Speed Select 0
Core Speed Select
Bit 3
NSTOP
Bit 3
BOT
Brown-Out Threshold
BOT = 1, low brown-out voltage threshold (3.0 V)
BOT = 0, high brown-out voltage threshold (4.0 V)
Oscillator Select 1
Oscillator Select 0
resistor at OSC1 generates SYSCL dependent on the setting of OS0
and OS1 in the system configuration register
Bit 2
CCS
Bit 2
–
CSS0
0
1
0
1
Bit 1
CSS1
Bit 1
OS1
Bit 0
CSS0
Bit 0
OS0
Divider
Primary register address: ’3’hex
Reset value: 1x11b
Auxiliary register address:
Reset value: 1111b
16
8
4
2
Reset value
4708D–4BMCU–09/05
Note
’3’hex
–
–
–