PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 177

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
PROPRIETARY AND CONFIDENTIAL
status is written into the FIFO. This is done to provide alignment of link down
status with the data read from the FIFO. It is up to the controlling processor to
check the COLS bit in the RDLC Status register for a change in the link status. If
the COLS bit is set to logic 1, the FIFO must be emptied to determine the current
link status. The first flag and abort status encoded in the PBS bits is used to set
and clear a Link Active software flag.
When the last byte of a properly terminated packet is received, an interrupt is
generated. While the RDLC Status register is being read the PKIN bit will be
logic 1. This can be a signal to the external processor to empty the bytes
remaining in the FIFO or to just increment a number-of-packets-received count
and wait for the FIFO to fill to a programmable level. Once the RDLC Status
register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is
read immediately after the last packet byte is read from the FIFO, the PBS[2] bit
will be logic 1 and the CRC and non-integer byte status can be checked by
reading the PBS[1:0] bits.
When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must
be emptied to remove this source of interrupt.
The RDLC can be used in a polled or interrupt driven mode for the transfer of
frame data. In the polled mode, the processor controlling the RDLC must
periodically read the RDLC Status register to determine when to read the RDLC
Data register. In the interrupt driven mode, the processor controlling the RDLC
uses the TEMAP-84 INTB output and the TEMAP-84 Master Interrupt Source
registers to determine when to read the RDLC Data register.
In the case of interrupt driven data transfer from the RDLC to the processor, the
INTB output of the TEMAP-84 is connected to the interrupt input of the
processor. The processor interrupt service routine verifies what block generated
the interrupt by reading the TEMAP-84 Master Interrupt Source register followed
by one of the second level master interrupt source registers to identify one of
the 3 HDLC receivers as the interrupt source. Once it has identified that the
RDLC has generated the interrupt, it processes the data in the following order:
1. Read the RDLC Status register. The INTR bit should be logic 1.
2. If OVR = 1, then discard the last frame and go to step 1. Overrun causes a
3. If COLS = 1, then set the EMPTY FIFO software flag.
4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be
reset of FIFO pointers. Any packets that may have been in the FIFO are lost.
emptied as soon as a complete packet is received, set the EMPTY FIFO
ISSUE 1
165
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84