PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 172

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
12.6 Using the Internal DS3 or E3 HDLC Transmitter
PROPRIETARY AND CONFIDENTIAL
The bit error rate for T1 ESF can be calculated from the one-second PMON
CRCE count by the following equation:
Bit Error Rate = 1 - 10
Figure 16
For T1 SF format, the CRCE and FER counts are identical, but the FER counter
is smaller and should be ignored.
Figure 17
It is important to note that access rate to the TDPR registers is limited by the rate
of the internal DS3/E3 clock. Consecutive accesses to the TDPR Configuration,
TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07
0
- CRCE Count vs. BER (T1 ESF mode)
- CRCE Count vs. BER (T1 SF mode)
50
20
18
16
14
12
10
0
4
2
8
6
ISSUE 1
0
100
æ
ç
ç
ç
ç ç
è
log
æ
ç
è
200
1
−
24
8000
*
24
193
150
BEE
Bit Error Event Count Per Second
400
CRCE
ö
÷
ö
Many 1 Second Intervals
Average Count Over
200
600
160
250
800
1000
300
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
1200
350
AND M13 MULTIPLEXER
PM5366 TEMAP-84