PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 167

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
PROPRIETARY AND CONFIDENTIAL
M x : M-Frame Alignment Signal
F x : M-Subframe Alignment Signal
C x : C-Bit Channels
• Transmit: The TEMAP-84 generates the M-frame alignment signal (M1 = 0,
• Receive: The TEMAP-84 finds M-frame alignment by searching for the F-
• Transmit: The TEMAP-84 generates the M-Subframe Alignment signal
• Receive: The TEMAP-84 finds M-frame alignment by searching for the F-
• Transmit: When configured for M23 applications, the C-bits used for
• Receive: The CBITV register bit in the DS3 FRMR Status register is used
M2 = 1, M3 = 0).
bits and the M-bits. Out-of-frame is removed if the M-bits are correct for
three consecutive M-frames while no discrepancies have occurred in the F-
bits. M-bit errors are counted in the DS3 PMON Framing Bit Error Event
Count registers. When one or more M-bit errors are detected in 3 out of 4
consecutive M-frames, an out-of-frame defect is asserted (if MBDIS in the
DS3 Framer Configuration register is a logic 0).
(F1=1, F2=0, F3=0, F4=1).
bits and the M-bits. Out-of-frame is removed if the M-bits are correct for
three consecutive M-frames while no discrepancies have occurred in the F-
bits. F-bit errors are counted in the DS3 PMON Framing Bit Error Event
Count registers. An out-of frame defect is asserted if 3 F-bit errors out of 8
or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the
DS3 FRMR Configuration register).
stuffing indication. When configured for C-bit parity applications, the C-bit
Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to
logic 1. The third C-bit in M-subframe 1 provides a far-end alarm and
control (FEAC) signal. The FEAC channel is sourced by the DS3 XBOC
block. The 3 C-bits in M-subframe 3 carry path parity information. The
value of these 3 C-bits is the same as that of the P-bits. The 3 C-bits in M-
subframe 4 are the FEBE bits. FEBE transmission is controlled by the
DFEBE bit in the DS3 TRAN Diagnostic register and by the detection of
receive framing bit and path parity errors. The 3 C-bits in M-subframe 5
contain the 28.2 kbit/s path maintenance datalink. These bits are inserted
from the DS3 TDPR HDLC controller. The C-bits in M-subframes 2, 6, and
7 are unused and are set to logic 1.
to report the state of the C-bit parity ID bit, and hence whether a M23 or C-
bit parity DS3 signal stream is being received. The FEAC channel on the
third C-bit in M-subframe 1 is detected by the DS3 RBOC block. Path
parity errors and detected FEBEs on the C-bits in M-subframes 3 and 4 are
reported in the DS3 PMON Path Parity Error Event Count and FEBE Event
ISSUE 1
155
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84