PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 176

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
If all bytes in the packet have been sent, then set the EOM bit in the TDPR
Configuration register to logic 1. Go to step 1.
12.7 Using the Internal DS3 or E3 Data Link Receiver
PROPRIETARY AND CONFIDENTIAL
1. Wait until data is available to be transmitted, then go to step 2.
2. Read the TDPR Interrupt Status register.
3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written.
4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit.
5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be
6. If more data bytes are to be transmitted in the packet, then go to step 2.
It is important to note that the access rate to the RDLC registers is limited by the
rate of the internal DS3 or E3 clock. Consecutive accesses to the RDLC Status
and RDLC Data registers should be accessed at a rate no faster than 1/10 that
of the selected RDLC high-speed system clock. This time is used by the high-
speed system clock to sample the event and update the FIFO status.
Instantaneous variations in the DS3 or E3 frequencies (e.g. jitter in the receive
line clock) must be considered when determining the procedure used to read
RDLC registers.
On power up of the system, the RDLC should be disabled by setting the EN bit in
the Configuration Register to logic 0 (default state). The RDLC Interrupt Control
register should then be initialized to enable the INTB output and to select the
FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not
set to logic 1, the RDLC Status register must be continuously polled to check the
interrupt status (INTR) bit.
After the RDLC Interrupt Control register has been written, the RDLC can be
enabled at any time by setting the EN bit in the RDLC Configuration register to
logic 1. When the RDLC is enabled, it will assume the link status is idle (all
ones) and immediately begin searching for flags. When the first flag is found, an
interrupt will be generated, and a dummy byte will be written into the FIFO buffer.
This is done to provide alignment of link up status with the data read from the
FIFO. When an abort character is received, another dummy byte and link down
Continue polling the TDPR Interrupt Status register until either FULL=0 or
BLFILL=1. Then, go to either step 4 or 5 depending on implementation
preference.
Write the data into the TDPR Transmit Data register. Go to step 6.
written. Write the data into the TDPR Transmit Data register. Go to step 6.
ISSUE 1
164
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84