ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 59

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
7.6.2
External interrupt control register (EICR)
Table 21.
EICR
7:6
4:3
Bit
5
2
1
0
7
IS1[1:0]
IS2[1:0]
Name
TLIS
TLIE
IS1[1:0]
IPB
IPA
RW
EICR register description
ei2 and ei3 sensitivity
Interrupt polarity for port B
ei0 and ei1 sensitivity
Interrupt polarity for port A
TLI sensitivity
TLI enable
6
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 (port B3..0) (see
- ei3 (port B7..4) (see
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
- ei0 (port A3..0) (see
- ei1 (port F2..0) (see
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by
software only when TLIE bit is cleared.
0: Falling edge
1: Rising edge
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set
and cleared by software.
0: TLI disabled
1: TLI enabled
Note: A parasitic interrupt can be generated when clearing the TLIE bit.
IPB
RW
5
Doc ID 13829 Rev 1
Table
Table
Table
Table
4
IS2[1:0]
25)
22)
23)
24)
RW
Function
3
RW
IPA
2
Reset value: 0000 0000 (00h)
TLIS
RW
1
Interrupts
TLIE
RW
0
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