ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 132

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Serial peripheral interface (SPI)
14.8.2
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Table 66.
Table 67.
Control/status register (SPICSR)
Table 68.
SPICSR
Bit
1:0 SPR[1:0]
Bit
7
6
5
SPIF
RO
7
WCOL
Name
SPIF
OVR
Name
SPICR register description (continued)
SPI master mode SCK frequency
SPICSR register description
Serial clock
Serial Peripheral Data Transfer Flag
Write Collision status
SPI Overrun error
WCOL
f
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see
0: No write collision occurred.
1: A write collision has been detected.
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see
condition (OVR) on page
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
RO
f
f
f
CPU
Serial Clock Frequency
f
f
CPU
CPU
CPU
6
CPU
CPU
These bits are set and cleared by software. Used with the SPR2 bit, they select
the baud rate of the SPI serial clock SCK output by the SPI in master mode.
Note: These 2 bits have no effect in slave mode.
/128
/16
/32
/64
/4
/8
OVR
RO
5
Doc ID 13829 Rev 1
MODF
128). An interrupt is generated if SPIE = 1 in SPICR
RO
4
SPR2
1
0
0
1
0
0
Reserved
Function
Function
3
-
SOD
RW
SPR1
2
0
0
0
1
1
1
Reset value: 0000 0000 (00h)
Figure
SSM
RW
1
ST72321xx-Auto
60).
Overrun
SPR0
0
0
1
0
0
1
SSI
RW
0