ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 160

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

I2C bus interface (I2C)
Note:
Note:
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Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
●
●
Then the master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
●
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see
EV6).
Next, the master must enter Receiver or Transmitter mode.
In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
●
●
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see
To close the communication: Before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see
When the acknowledge bit is received, the interface sets:
●
To close the communication: After writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event:
–
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
EVF and BTF bits with an interrupt if the ITE bit is set.
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Doc ID 13829 Rev 1
Figure 68: Transfer sequencing
Figure 68: Transfer sequencing
Figure 68: Transfer sequencing
Figure 68: Transfer sequencing
EV9).
EV7).
EV8).
ST72321xx-Auto