ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 163

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ST72321AR9-Auto

Manufacturer Part Number
ST72321AR9-Auto
Description
8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72321AR9-Auto

Hdflash Endurance
100 cycles, data retention 20 years
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt, Wait and Slow
ST72321xx-Auto
16.5
16.6
Note:
Low power modes
Table 81.
Interrupts
Figure 69. Interrupt control logic diagram
Table 82.
The I
They generate an interrupt if the corresponding Enable Control bit is set and the I-bit in the
CC register is reset (RIM instruction).
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
* EVF can also be set by EV6 or an error from the SR2 register.
Mode
Wait
Halt
2
STOPF
C interrupt events are connected to the same interrupt vector (see
ADD10
BERR
ARLO
*
ADSL
BTF
SB
AF
No effect on I
I
I
In Halt mode, the I
I
Halt mode” capability.
2
2
2
C interrupts cause the device to exit from Wait mode.
C registers are frozen.
C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Effect of low power modes on I
I
2
C interrupt control/wake-up capability
Interrupt event
2
C interface.
2
C interface is inactive and does not acknowledge data on the bus. The
Doc ID 13829 Rev 1
ITE
2
Event flag
C
Effect
ADSEL
STOPF
ADD10
BERR
ARLO
BTF
SB
AF
control bit
Enable
ITE
I2C bus interface (I2C)
Exit from
Interrupts
Wait
Yes
INTERRUPT
Exit from
chapter).
EVF
Halt
163/243
No

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