ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 40

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Supply, reset and clock management
6.5
6.5.1
Caution:
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Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
●
●
●
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of three phases as shown in
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●
●
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset block diagram
External RESET source pulse
Internal LVD RESET (low voltage detection)
Internal WATCHDOG RESET
Active phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by option byte)
RESET vector fetch
RESET
V
DD
R
ON
Doc ID 13829 Rev 1
Filter
Section 21.1.1: Flash configuration on page
GENERATOR
PULSE
Figure
WATCHDOG RESET
LVD RESET
12:
INTERNAL
RESET
ST72321xx-Auto
Figure
11:
223).