ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 41

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
6.5.2
6.5.3
6.5.4
Figure 12. RESET sequence phases
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See
characteristics on page
A RESET signal originating from an external source must have a duration of at least
t
therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in
Electrical
If the external RESET pulse is shorter than t
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in
device RESET pin acts as an output that is pulled low during at least t
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
conditions on page
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
V
The LVD filters spikes on V
h(RSTL)in
DD
< V
Power-on RESET
Voltage drop RESET
IT-
in order to be recognized (see
characteristics.
(falling edge) as shown in
ACTIVE PHASE
Figure
188).
207for more details.
13). Starting from the external RESET pulse recognition, the
DD
larger than t
Doc ID 13829 Rev 1
256 or 4096 CLOCK CYCLES
Figure
DD
INTERNAL RESET
Figure
g(VDD)
RESET
supply can generally be provided by an external
13.
w(RSTL)out
OSC
13). This detection is asynchronous and
to avoid parasitic resets.
frequency (see
Supply, reset and clock management
(see short ext. Reset in
Section 19.9: Control pin
Section 19.3: Operating
DD
< V
w(RSTL)out
VECTOR
FETCH
IT+
ON
(rising edge) or
Section 19:
weak pull-up
Figure
.
DD
is over
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13),