AD7712 Analog Devices, AD7712 Datasheet - Page 22

no-image

AD7712

Manufacturer Part Number
AD7712
Description
CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with 2 Analog Input Channels
Manufacturer
Analog Devices
Datasheet

Specifications of AD7712

Resolution (bits)
24bit
# Chan
2
Sample Rate
19.5kSPS
Interface
Ser
Analog Input Type
Diff-Bip,Diff-Uni,SE-Bip
Ain Range
Bip (Vref) x 4,Bip (Vref)/(PGA Gain),Bip 10V,Bip 20V,Uni (Vref) x 4,Uni (Vref)/(PGA Gain),Uni 10V,Uni 20V
Adc Architecture
Sigma-Delta
Pkg Type
DIP,SOIC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7712AARZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7712AN
Manufacturer:
TI
Quantity:
25
Part Number:
AD7712AN
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7712ANZ
Manufacturer:
ALTERA
Quantity:
300
Part Number:
AD7712AQ
Manufacturer:
INTEL
Quantity:
4
Part Number:
AD7712AR
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7712ARZ
Manufacturer:
AD
Quantity:
2
Part Number:
AD7712ARZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD7712
Figure 13a shows a read operation from the AD7712 where
RFS remains low for the duration of the data word transmis-
sion. With DRDY low, the RFS input is brought low. The input
SCLK signal should be low between read and write operations.
RFS going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the DRDY line high. This rising edge of DRDY turns off
the serial data output.
Figure 13b shows a timing diagram for a read operation where
RFS returns high during the transmission of the word and
returns low again to access the rest of the data-word. Timing
parameters and functions are very similar to that outlined for
Figure 13b. External Clocking Mode, Output Data Read Operation ( RFS Returns High during Read Operation)
SDATA (O)
SDATA (O)
DRDY (O)
DRDY (O)
SCLK (I)
SCLK (I)
RFS (I)
RFS (I)
A0 (I)
A0 (I)
Figure 13a. External Clocking Mode, Output Data Read Operation
t
20
t
t
20
22
t
22
t
t
24
24
t
t
MSB
26
25
MSB
t
25
–22–
t
27
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when RFS returns high in the middle
of transferring a word.
RFS should return high during a low time of SCLK. On the
rising edge of RFS, the SDATA output is turned off. DRDY
remains low and will remain low until all bits of the data-word
are read from the AD7712, regardless of the number of times
RFS changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS, the next bit (BIT N + 1) may appear on the data bus
before RFS goes high. When RFS returns low again, it activates
the SDATA output. When the entire word is transmitted, the
DRDY line will go high, turning off the SDATA output as per
Figure 13a.
BIT N
t
26
THREE-STATE
t
t
27
30
t
31
LSB
t
24
t
29
t
21
BIT N+1
t
28
t
THREE-STATE
23
t
25
REV. F

Related parts for AD7712