AD7712 Analog Devices, AD7712 Datasheet - Page 15

• Manufacturer Part Number: AD7712
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with 2 Analog Input Channels
• Manufacturer: Analog Devices

Specifications of AD7712

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip
• Ain Range: Bip (Vref) x 4,Bip (Vref)/(PGA Gain),Bip 10V,Bip 20V,Uni (Vref) x 4,Uni (Vref)/(PGA Gain),Uni 10V,Uni 20V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Antialias Considerations
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sample frequency (n
n = 1, 2, 3 . . . ). This means that there are frequency bands,
± f
where noise passes unattenuated to the output. However, due to
the AD7712’s high oversampling ratio, these bands occupy only
a small fraction of the spectrum, and most broadband noise is
filtered. In any case, because of the high oversampling ratio, a
simple, RC, single-pole filter is generally sufficient to attenuate
the signals in these bands on the analog input and thus provide
adequate antialiasing filtering.
If passive components are placed in front of the AIN1 input of the
AD7712, care must be taken to ensure that the source impedance
is low enough so as not to introduce gain errors in the system. The
dc input impedance for the AIN1 input is over 1 GΩ. The input
appears as a dynamic load that varies with the clock frequency
and with the selected gain (see Figure 7). The input sample
rate, as shown in Table III, determines the time allowed for the
analog input capacitor, C
result in a longer charge time for this capacitor, which may result
in gain errors being introduced on the analog inputs. Table IV
shows the allowable external resistance/capacitance values
such that no gain error to the 16-bit level is introduced, while
Table V shows the allowable external resistance/capacitance
values such that no gain error to the 20-bit level is introduced.
Both inputs of the differential input channels (AIN1) look into
similar input circuitry.
REV. F
3 dB
wide (f
AIN
3 dB
Figure 7. AIN1 Input Impedance
is cutoff frequency selected by FS0 to FS11),
SWITCHING FREQUENCY DEPENDS ON
f
CLKIN
AND SELECTED GAIN
(7k
(11.5pF TYP)
IN
R
INT
, to be charged. External impedances
TYP)
C
INT
V
BIAS
IMPEDANCE
>1G
HIGH
19.5 kHz, where
–15–
Gain
1
2
4
8–128 17.6 kΩ 4.8 kΩ
Gain
1
2
4
8–128 13.4 kΩ 3.6 kΩ
The numbers in Tables IV and V assume a full-scale change on
the analog input. In any case, the error introduced due to longer
charging times is a gain error that can be removed using the
system calibration capabilities of the AD7712 provided that the
resultant span is within the span limits of the system calibration
techniques for the AD7712.
The AIN2 input contains a resistive attenuation network as
outlined in Figure 8. The typical input impedance on this input
is 44 kΩ. As a result, the AIN2 input should be driven from a
low impedance source.
Table IV. Typical External Series Resistance That Will Not
Introduce 16-Bit Gain Error
Table V. Typical External Series Resistance That Will Not
Introduce 20-Bit Gain Error
0
184 kΩ
88.6 kΩ 22.1 kΩ 13.2 kΩ 3.6 kΩ
41.4 kΩ 10.6 kΩ 6.3 kΩ
0
145 kΩ
70.5 kΩ 16.9 kΩ 10 kΩ
31.8 kΩ 8.0 kΩ
AIN2
Figure 8. AIN2 Input Impedance
External Capacitance (pF)
50
45.3 kΩ 27.1 kΩ 7.3 kΩ
External Capacitance (pF)
50
34.5 kΩ 20.4 kΩ 5.2 kΩ
33k
11k
100
2.9 kΩ
100
4.8 kΩ
2.2 kΩ
MODULATOR
500
1.7 kΩ
790 Ω
500
2.5 kΩ
1.2 kΩ
550 Ω
CIRCUIT
V
BIAS
AD7712
1000
4.1 kΩ
2.0 kΩ
970 Ω
440 Ω
1000
2.8 kΩ
1.4 kΩ
670 Ω
300 Ω
5000
1.1 kΩ
560 Ω
270 Ω
120 Ω
5000
700 Ω
350 Ω
170 Ω
80 Ω