AD7712 Analog Devices, AD7712 Datasheet - Page 2

• Manufacturer Part Number: AD7712
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with 2 Analog Input Channels
• Manufacturer: Analog Devices

Specifications of AD7712

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip
• Ain Range: Bip (Vref) x 4,Bip (Vref)/(PGA Gain),Bip 10V,Bip 20V,Uni (Vref) x 4,Uni (Vref)/(PGA Gain),Uni 10V,Uni 20V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7712–SPECIFICATIONS
REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications T
Parameter
STATIC PERFORMANCE
ANALOG INPUTS/REFERENCE INPUTS
NOTES
10
11
12
1
2
3
4
5
6
7
8
9
or background calibration.
source resistance depends on the selected gain (see Tables IV and V).
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV
V
This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the Static Performance section.
The reference input voltage range may be restricted by the input voltage range requirement on the V
Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.
Applies after calibration at the temperature of interest.
Positive full-scale error applies to both unipolar and bipolar input ranges.
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
These numbers are guaranteed by design and/or characterization.
This common-mode voltage range is allowed, provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV
The AIN1 analog input presents a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended
The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
No Missing Codes
Output Noise
Integral Nonlinearity @ 25°C
Positive Full-Scale Error
Full-Scale Drift
Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
Bipolar Zero Drift
Gain Drift
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
AIN1/REF IN
Analog Inputs
Reference Inputs
REF
T
T
DC Input Leakage Current @ 25°C
T
Sampling Capacitance
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range
Input Sampling Rate, f
AIN1 Input Voltage Range
AIN2 Input Voltage Range
AIN2 DC Input Impedance
AIN2 Gain Error
AIN2 Gain Drift
AIN2 Offset Error
AIN2 Offset Drift
REF IN(+) – REF IN(–) Voltage
Input Sampling Rate, f
= REF IN(+) – REF IN(–).
MIN
MIN
MIN
to T
to T
to T
MAX
MAX
MAX
8
5
5
2, 4
11
11
5
2, 4
2, 3, 4
6
S
S
9
9
6
6
5
2
7
@ 25°C
6
6
12
6
A, S Versions
24
22
18
15
12
See Tables I and II
± 0.0015
± 0.003
1
0.3
0.5
0.25
0.5
0.25
2
± 0.003
± 0.006
1
0.3
100
100
10
1
20
100
90
150
150
V
See Table III
0 V to V
± V
0 V to 4
± 4
30
± 0.05
1
10
20
2.5 to 5
f
CLK IN
SS
REF
to AV
V
/256
REF
REF
DD
(AV
V
10
REF
DD
1
10
= +5 V
Unit
Bits min
Bits min
Bits min
Bits min
Bits min
% FSR max
% FSR max
µV/°C typ
µV/°C typ
µV/°C typ
µV/°C typ
µV/°C typ
µV/°C typ
ppm/°C typ
% FSR max
% FSR max
µV/°C typ
µV/°C typ
dB min
dB min
pA max
nA max
pF max
dB min
dB min
dB min
dB min
V min to V max
V max
V max
V max
V max
kΩ
% typ
ppm/°C typ
mV max
µV/°C typ
V min to V max
–2–
5%; DV
DD
MIN
= +5 V
to T
BIAS
MAX
Conditions/Comments
Guaranteed by Design. For Filter Notches ≤ 60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches ≤ 60 Hz
Typically ± 0.0003%
Excluding Reference
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Excluding Reference
Typically ± 0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02
For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02
At dc and AV
At dc and AV
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02
For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
Additional Error Contributed by Resistor Attenuator
Additional Drift Contributed by Resistor Attenuator
Additional Error Contributed by Resistor Attenuator
For Specified Performance. Part Is Functional with
Lower V
input.
, unless otherwise noted.)
5%; V
DD
REF
+ 30 mV or more negative than V
SS
Voltages
= 0 V or –5 V
DD
DD
= 5 V
= 10 V
DD
+ 30 mV and V
5%; REF IN(+) = +2.5 V;
SS
– 30 mV.
SS
– 30 mV.
REV. F
f
f
f
f
NOTCH
NOTCH
NOTCH
NOTCH