AD7712 Analog Devices, AD7712 Datasheet - Page 13

• Manufacturer Part Number: AD7712
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with 2 Analog Input Channels
• Manufacturer: Analog Devices

Specifications of AD7712

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip
• Ain Range: Bip (Vref) x 4,Bip (Vref)/(PGA Gain),Bip 10V,Bip 20V,Uni (Vref) x 4,Uni (Vref)/(PGA Gain),Uni 10V,Uni 20V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

The AD7712 provides a number of calibration options that can
be programmed via the on-chip control register. A calibration
cycle can be initiated at any time by writing to this control regis-
ter. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components can also be included in
the calibration loop to remove offset and gain errors in the input
channel using the system calibration mode. Another option is a
background calibration mode where the part continuously
performs self-calibration and updates the calibration coeffi-
cients. Once the part is in this mode, the user does not have to
worry about issuing periodic calibration commands to the
device or asking the device to recalibrate when there is a change
in the ambient temperature or power supply voltage.
The AD7712 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the device’s
calibration coefficients and also to write its own calibration
coefficients to the part from prestored values in E
gives the microprocessor much greater control over the AD7712’s
calibration procedure. It also means that the user can verify that
the device has performed its calibration correctly by comparing
the coefficients after calibration with prestored values in
E
The AD7712 can be operated in single-supply systems, provided
that the analog input voltage on the AIN1 input does not go
more negative than –30 mV. For larger bipolar signals on the
AIN1 input, a V
operation or low power systems, the AD7712 offers a standby
mode (controlled by the STANDBY pin) that reduces idle
power consumption to typically 100 µW.
THEORY OF OPERATION
The general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:
•
•
•
•
•
•
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
REV. F
2
A sample-hold amplifier
A differential amplifier or subtracter
An analog low-pass filter
A 1-bit A/D converter (comparator)
A 1-bit DAC
A digital low-pass filter
PROM.
S/H AMP
Figure 4. General Sigma-Delta ADC
SS
of –5 V is required by the part. For battery
LOW-PASS
ANALOG
FILTER
DAC
COMPARATOR
DIGITAL DATA
2
PROM. This
DIGITAL
FILTER
–13–
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
A 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7712 samples the input signal at a frequency of 39 kHz
or greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy
to frequencies outside the bandwidth of interest. The noise
performance is thus improved from this 1-bit level to the perfor-
mance outlined in Tables I and II and in Figure 2.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data-word using a
digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first-order sigma-
delta ADC is shown in Figure 5. This contains only a first order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: charge-balancing ADCs.
It consists of a differential amplifier (whose output is the differ-
ence between the analog input and the output of a 1-bit DAC),
an integrator, and a comparator. The term charge balancing,
comes from the fact that this system is a negative feedback loop
that tries to keep the net charge on the integrator capacitor at
zero by balancing charge injected by the input voltage with
charge injected by the 1-bit DAC. When the analog input is
zero, the only contribution to the integrator output comes from
the 1-bit DAC. For the net charge on the integrator capacitor to
be zero, the DAC output must spend half its time at +FS and
half its time at –FS. Assuming ideal components, the duty cycle
of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7712 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up, or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
V
IN
SNR = (6.02 3 number of bits + 1.76) dB
Figure 5. Basic Charge-Balancing ADC
DIFFERENTIAL
AMPLIFIER
+FS
–FS
DAC
COMPARATOR
AD7712