AD7712 Analog Devices, AD7712 Datasheet
AD7712
Specifications of AD7712
Available stocks
Related parts for AD7712
AD7712 Summary of contents
Page 1
... The AD7712 allows the user to read and to write the on-chip calibration registers. This means that the microcontroller has much greater control over the calibration procedure. ...
Page 2
... REF IN(+) – REF IN(–). REF 11 This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset drift on the AIN2 input is 4 times the value given in the Static Performance section. 12 The reference input voltage range may be restricted by the input voltage range requirement on the V ...
Page 3
... Input Span AIN2 15 Positive Full-Scale Calibration Limit 15 Negative Full-Scale Calibration Limit 17 Offset Calibration Limit 15 Input Span NOTES 13 The AD7712 is tested with the following V BIAS with and V = – BIAS 14 Guaranteed by design, not production tested. 15 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will output all 0s ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7712 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... The AD7712 is specified with a 10 MHz clock for AV than 10 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5 ...
Page 6
... Data Valid to SCLK Hold Time PIN CONFIGURATION DIP and SOIC SCLK DGND 1 24 MCLK MCLK OUT SDATA DRDY 4 21 SYNC 5 20 RFS AD7712 MODE TFS 6 19 TOP VIEW (Not to Scale) AIN1(+) 7 AGND 18 AIN1(–) AIN2 8 17 STANDBY REF OUT REF IN(+) REF IN(– ...
Page 7
... Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. SYNC 5 Logic Input. Allows for synchronization of the digital filters when using a number of AD7712s. It resets the nodes of the digital filter. 6 MODE Logic Input ...
Page 8
... AD7712 can accept and still accurately calibrate offset. Full-Scale Calibration Range This is the range of voltages that the AD7712 can accept in the system calibration mode and still correctly calibrate full scale. Input Span In system calibration schemes, two voltages applied in sequence to the AD7712’ ...
Page 9
... Activate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, then the AD7712 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. Its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature ...
Page 10
... FS11 and is in the range 19 to 2,000. With the nominal f 10 MHz, this results in a first notch frequency range from 9. 1.028 kHz. To ensure correct operation of the AD7712, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. ...
Page 11
... Effective Resolution* (Bits) Gain of Gain of Gain 21 19.5 18.5 18.5 18.5 15.5 15 –11– AD7712 V /GAIN, i.e., the input full REF Gain of Gain of Gain 0.25 0.25 0.25 0.44 0.41 0.38 0.46 0.43 0.4 0.54 0.46 0.46 0.63 0.62 0.6 1.1 0.9 0.65 7 180 120 70 Gain of Gain of Gain ...
Page 12
... Figure 2b. Plot of Output Noise vs. Gain and Notch Frequency (Gains 128) The basic connection diagram for the part is shown in Figure 3. This shows the AD7712 in the external clocking mode with both the AV analog 5 V supply. Some applications will have separate supplies for both AV supply will exceed the 5 V digital supply (see the Power Supplies and Grounding section) ...
Page 13
... ADCs. Using the quantization noise formula for an ADC: SNR = (6.02 3 number of bits + 1.76 1-bit ADC or comparator yields an SNR of 7.78 dB. The AD7712 samples the input signal at a frequency of 39 kHz or greater (see Table III result, the quantization noise is spread over a much wider frequency than that of the band of interest ...
Page 14
... AD7712. For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7712 at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz. Post filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz ...
Page 15
... If passive components are placed in front of the AIN1 input of the AD7712, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. The dc input impedance for the AIN1 input is over 1 GΩ. The input appears as a dynamic load that varies with the clock frequency and with the selected gain (see Figure 7) ...
Page 16
... V of 2.5 V, the input voltage range on REF the AIN1(+) input AIN1(–) is 1.25 V and the AD7712 is configured for bipolar mode with a gain of 1 and 2.5 V, the analog input range on the AIN1(+) input is REF –1. +3.75 V. For the AIN2 input, the input signals are referenced to AGND ...
Page 17
... SYNC pulse to the voltage tracks BIAS AD7712 will reset the AD7712’s digital filter logic the SYNC line, with R, C time constant longer than the DV power-on time, will perform the SYNC function. line and V ...
Page 18
... MD2, MD1, MD0 of the control register. When invoked, the background calibration mode reduces the output data rate of the AD7712 by a factor of 6, while the –3 dB bandwidth remains unchanged. Its advantage is that the part is continually performing calibration and automatically updating its calibration coefficients ...
Page 19
... Figure 10 preferable that the common supply is the system’s analog 5 V supply also important that power is applied to the AD7712 before signals at REF IN, AIN, or the logic input pins in order to avoid excessive current. If separate supplies are used for the AD7712 and the system digital circuitry, then the AD7712 should be powered up first ...
Page 20
... SCLK output. With DRDY low, the RFS input is brought low. RFS going low enables the serial clock of the AD7712 and also places the MSB of the word on the serial data line. All subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock ...
Page 21
... The falling edge of TFS enables the internally generated SCLK output. The serial data to be loaded to the AD7712 must be valid on the rising edge of this SCLK signal. Data is clocked into the AD7712 on the rising edge of the SCLK signal, with the MSB transferred first ...
Page 22
... RFS, the SDATA output is turned off. DRDY remains low and will remain low until all bits of the data-word are read from the AD7712, regardless of the number of times RFS changes state during the read operation. Depending on the time between the falling edge of SCLK and the rising edge of RFS, the next bit (BIT may appear on the data bus before RFS goes high ...
Page 23
... TFS returns high in the middle of transferring a word. Data to be loaded to the AD7712 must be valid prior to the rising edge of the SCLK signal. TFS should return high during the low time of SCLK. After TFS returns low again, the next bit of the data-word to be loaded to the AD7712 is clocked in on next high level of the SCLK input ...
Page 24
... This depends on whether the first bit transmitted by the microprocessor is the MSB or the LSB. The AD7712 expects the MSB as the first bit in the data stream. In cases where the data is being read or being written in bytes and the data has to be reversed, the bits will have to be reversed for every byte. – ...
Page 25
... AD7712. The 8XC51 outputs the LSB first in a write operation while the AD7712 expects the MSB first, so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7712 outputs the MSB first during a read operation while the 8XC51 expects the LSB first ...
Page 26
... The AD7712 is configured for its external clocking mode, while the SPI port is used on the 68HC11, which is in its single-chip mode. The DRDY line from the AD7712 is connected to the Port PC2 input of the High 68HC11 so the DRDY line is polled by the 68HC11. The ...
Page 27
... COPLANARITY 0.10 REV. F through the 500 Ω resistor. The AD7712 can handle an input span as low as 3.2 though the nominal input voltage range for the input Therefore, the full span of the A/D converter can be used for measuring the current between 4 mA and 20 mA. ...
Page 28
... Revision History Location 3/04—Data Sheet changed from REV REV. F. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Deleted AD7712 to ADSP-2105 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Changes to AD7712 to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTLINE DIMENSIONS 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) ...