AD9874 Analog Devices, AD9874 Datasheet - Page 8

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9874–Typical Performance Characteristics
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f
T
TPC 1a. CDF of SSB Noise Figure
(VDDx = 3.0 V, High Bias
TPC 2a. CDF of IIP3 (VDDx = 3.0 V,
High Bias
TPC 3a. CDF of Dynamic Range
(VDDx = 3.0 V, High Bias
1
2
3
Data taken with Toko FSLM series 10 µH inductors.
High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
A
= 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
100
100
100
80
60
40
20
80
60
40
20
80
60
40
20
0
0
0
92
–3
–40 C
7.2
–40 C
2
93
)
7.5
–2
+85 C
DYNAMIC RANGE – dB
NOISE FIGURE – dB
94
7.8
+25 C
IIP3 – dBm
–1
8.1
95
+25 C
+25 C
0
8.4
96
2
2
)
)
–40 C
+85 C
+85 C
8.7
1
97
9.0
98
2
TPC 1b. SSB Noise Figure vs. Supply
(High Bias
TPC 2b. IIP3 vs. Supply (High Bias
TPC 3b. Dynamic Range vs. Supply
(High Bias
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
1.5
1.0
0.5
98
97
96
95
94
93
92
2.7
0
2.7
2.7
2
2
)
)
3.0
3.0
3.0
+85 C
–40 C
–8–
VDDx – V
VDDx – V
VDDx – V
+85 C
+25 C
–40 C
–40 C
+25 C
3.3
3.3
3.3
+85 C
CLK
+25 C
= 18 MSPS, f
3.6
3.6
3.6
2
)
IF
TPC 1c. SSB Noise Figure vs. Supply
(Low Bias
TPC 2c. IIP3 vs. Supply (Low Bias
TPC 3c. Dynamic Range vs. Supply
(Low Bias
= 109.56 MHz, f
–10
–12
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
98
97
96
95
94
93
92
–2
–4
–6
–8
2.7
0
2.7
2.7
+25 C
+85 C
3
3
)
)
LO
3.0
3.0
3.0
= 107.4 MHz,
+85 C
1
+25 C
VDDx – V
VDDx – V
VDDx – V
–40 C
+85 C
+25 C
–40 C
3.3
3.3
3.3
–40 C
REV. A
3
3.6
3.6
3.6
)