AD9874 Analog Devices, AD9874 Datasheet - Page 21

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

CLOCK SYNTHESIZER
The clock synthesizer is a fully programmable integer-N PLL
capable of 2.2 kHz resolution at clock input frequencies up to
18 MHz and reference frequencies up to 25 MHz. It is similar
to the LO synthesizer described in Figure 5 with the following
exceptions:
• It does not include an 8/9 prescaler nor an A counter.
• It includes a negative-resistance core that, when used in conjunc-
The 14-bit reference counter and 13-bit N-divider counter can
be programmed via registers CKR and CKN. The clock
frequency, f
equation
The charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the equation:
The fast acquire subcircuit of the charge pump is controlled by
the CKFA register in the same manner as the LO synthesizer is
controlled by the LOFA register. An on-chip lock detect func-
tion (enabled by the CKF bit) automatically increases the
output current for faster settling during channel changes. The
synthesizer may also be disabled using the CK standby bit
located in the STBY register.
The AD9874 clock synthesizer circuitry includes a negative-
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 7a shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
REV. A
V
f
OSC
CM
tion with an external LC tank and varactor, serves as the VCO.
= VDDC – R
> 1/{2
I
f
CLK
Figure 7a. External Loop Filter, Varactor, and LC
Tank Are Required to Realize a Complete Clock
Synthesizer
PUMP
IOUTC
=
(L
CLK
=
(
BIAS
OSC
CKN CKR
R
(
F
CKI
, is related to the reference frequency by the
FILTER
LOOP
C
C
(C
I
Z
P
BIAS
VARACTOR
AD9874
+
> 1.6V
1
CLK OSC. BIAS
)
R
×
D
)
//C
0 625
×
.
OSC
f
C
REF
C
OSC
))
VAR
1/2
mA
}
2
CLKP
L
OSC
0.40 mA, OR 0.65 mA
I
BIAS
VDDC = 3.0 V
R
0.1 F
CLKN
BIAS
= 0.15 mA, 0.25 mA,
(5)
(6)
–21–
is approximately determined by L
capacitance of C
C
ensure proper locking of the clock synthesizer.
The bias, I
grammable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. R
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note that if an external
CLK source or VCO is used, the clock oscillator must be dis-
abled via the CKO standby bit.
The phase noise performance of the clock synthesizer is depen-
dent on several factors, including the CLK oscillator I
setting, charge pump setting, loop filter component values, and
internal f
phase noise attributed to the clock synthesizer varies (relative to
an external f
pump setting for a –31 dBm IFIN signal at 73.35 MHz with an
external LO signal at 71.1 MHz. Figure 7b shows that the opti-
mum phase noise is achieved with the highest I
setting, while Figure 7c shows that the higher charge pump
values provide the optimum performance for the given loop
filter configuration. The AD9874 clock synthesizer and oscilla-
tor were set up to provide an f
f
were selected for the synthesizer: R
C
C
REF
Figure 7b. CLK Phase Noise vs. I
(IF = 73.35 MHz, IF = 71.1 MHz, IFIN = –31 dBm,
f
CKI = 7, CLR = 56, and CLN = 60 with f
CLK
VAR
Z
VAR
= 0.68 µF, C
of 16.8 MHz. The following external component values
= 18 MHz, f
should be selected to provide a sufficient tuning range to
= Toshiba 1SV228 Varactor.
–100
–110
–120
–130
–140
–10
–20
–30
–40
–50
–60
–70
–80
–90
REF
0
–25
BIAS
CLK
setting. Figures 7b and 7c show how the measured
, of the negative-resistance core has four pro-
–20
) as a function of the I
P
OSC
REF
= 0.1 µF, C
CKO = 1
–15
and C
= 16.8 MHz) (CLK SYN Settings:
CKO = 0
–10
FREQUENCY OFFSET – kHz
VAR
OSC
–5
. As a result, L
CLK
BIAS
= 91 pF, L
OSC
of 18 MHz from an external
0
should be selected so the
BIAS
F
and the series equivalent
BIAS
= 390 Ω, R
5
Setting (CKO)
CKO = 2
CKO = 3
setting and charge
REF
OSC
10
OSC
= 300 kHz)
EXT CLK
BIAS
= 1.2 µH, and
AD9874
15
, C
D
(CKO)
OSC
= 2 kΩ,
20
, and
BIAS
25