AD9874 Analog Devices, AD9874 Datasheet - Page 32

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9874
Figure 22b plots the nominal system NF with 16-bit output
data as a function of AGC in both narrow-band and wideband
mode. In wideband mode, the NF curve is virtually unchanged
relative to the 24-bit output data because the output SNR
before truncation is always less than the 96 dB SNR that 16-bit
data can support.
However, in narrow-band mode, where the output SNR
approaches or exceeds the SNR that can be supported with 16-bit
data, the degradation in system NF is more severe. Further-
more, if the signal processing within the DSP adds noise at the
level of an LSB, the system noise figure can be degraded even
more than Figure 22b shows. For example, this could occur in a
fixed 16-bit DSP whose code is not optimized to process the
AD9874’s 16-bit data with minimal quantization effects. To
limit the quantization effects within the AD9874, the 24-bit
data undergoes noise shaping just prior to 16-bit truncation,
thus reducing the in-band quantization noise by 5 dB (with 23
oversampling). This explains why 98.8 dBFS SNR performance
is still achievable with 16-bit data in a 10 kHz BW.
Figure 22b. Nominal System Noise Figure and Peak SNR
vs. AGCG Setting (f
16-bit I/Q data)
17
16
15
14
13
12
11
10
9
8
Figure 23a. Total In-Band Noise + Spur Power with No Signal Applied as a Function of the LO Frequency
(f
0
SNR = 94.1dBFS
CLK
SNR = 83dBFS
= 18 MHz and Output Signal Bandwidth of 150 kHz)
IF
BW = 150kHz
3
–50
–60
–70
–80
–90
= 73.35 MHz, f
VGA ATTENUATION – dB
0
BW = 50kHz
BW = 10kHz
6
SNR = 98.8dBFS
CLK
50
= 18 MSPS, and
SNR = 89.9dBFS
9
1 2
100
–32–
LO FREQUENCY – MHz
APPLICATION CONSIDERATIONS
Frequency Planning
The LO frequency (and/or ADC clock frequency) must be
chosen carefully to prevent known internally generated spurs
from mixing down along with the desired signal, thus degrad-
ing the SNR performance. The major sources of spurs in the
AD9874 are the ADC clock and digital circuitry operating at
1/3 of f
important variable in determining which LO (and therefore
IF) frequencies are viable.
Many applications have frequency plans that take advantage of
industry-standard IF frequencies due to the large selection of
low cost crystal or SAW filters. If the selected IF frequency and
ADC clock rate result in a problematic spurious component, an
alternative ADC clock rate should be selected by slightly modi-
fying the decimation factor and CLK synthesizer settings (if
used) such that the output sample rate remains the same. Also,
applications requiring a certain degree of tuning range should
take into consideration the location and magnitude of these
spurs when determining the tuning range as well as optimum IF
and ADC clock frequency.
Figure 23a plots the measured in-band noise power as a func-
tion of the LO frequency for f
signal bandwidth of 150 kHz when no signal is present. Any LO
frequency resulting in large spurs should be avoided. As this
figure shows, large spurs result when the LO is f
away from a harmonic of 18 MHz (i.e., n f
problematic are LO frequencies whose odd order harmonics
(i.e., m f
mechanism is a result of the mixer being internally driven by a
squared-up version of the LO input consisting of the LO fre-
quency and its odd order harmonics. These spur frequencies
can be calculated from the relation
where m = 1, 3, 5... and n = 1, 2, 3...
A second source of spurs is a large block of digital circuitry that
is clocked at f
this spur source are given by:
where n = 1, 2, 3 ...
150
m f
f
LO
CLK
LO
LO
=
. Thus, the clock frequency (f
) mix with harmonics of f
=
f
CLK
CLK
(
n
/3
±
/3. Problematic LO frequencies associated with
1 8
200
+
n f
)
f
CLK
CLK
±
f
CLK
CLK
250
= 18 MHz and an output
8
CLK
to f
CLK
CLK
CLK
) is the most
CLK
f
/8. This spur
300
/8 = 2.25 MHz
CLK
/8). Also
REV. A
(12)
(13)