AD9874 Analog Devices, AD9874 Datasheet - Page 4

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9874
DIGITAL SPECIFICATIONS
f
Parameter
DECIMATOR
SPI-READ OPERATION (See Figure 1a)
SPI-WRITE OPERATION
SSI
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS
NOTES
1
2
3
4
5
Specifications subject to change without notice.
CLK
Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f
VDDx = 3.0 V.
Programmable in steps of 48 or 60.
CMOS output mode with C
Absolute Max and Min input/output levels are VDDH +0.3 V and –0.3 V.
I
OL
Decimation Factor
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
PC Clock Frequency
PC Clock Period (t
PC Clock HI (t
PC Clock LOW (t
PC to PD Setup Time (t
PC to PD Hold Time (t
PE to PC Setup Time (t
PC to PE Hold Time (t
PC Clock Frequency
PC Clock Period (t
PC Clock HI (t
PC Clock LOW (t
PC to PD Setup Time (t
PC to PD Hold Time (t
PC to PD (or DOUBT) Data Valid Time (t
PE to PD Output Valid to Hi-Z (t
CLKOUT Frequency
CLKOUT Period (t
CLKOUT Duty Cycle (t
CLKOUT to FS Valid Time (t
CLKOUT to DOUT Data Valid Time (t
Logic “1” Voltage (V
Logic “0” Voltage (V
Logic “1” Current (V
Logic “0” Current (V
Input Capacitance
Logic “1” Voltage (V
Logic “0” Voltage (V
3
= 18 MSPS, f
= 1 mA; specification is also dependent on Drive Strength setting.
(see Figure 2b)
IF
HI
HI
= 109.65 MHz, f
)
)
LOW
LOW
2
CLK
CLK
CLK
IH
IL
IH
IL
IH
IL
)
)
)
)
)
)
4
)
)
)
LOAD
)
)
H
DH
DH
S
DS
DS
)
3
HI,
)
3, 4, 5
)
(See Figure 1b)
)
)
)
t
= 10 pF and Drive Strength = 7.
LOW
V
)
)
LO
EZ
= 107.4 MHz, f
)
DV
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V,
)
DV
)
REF
= 16.8 MHz, unless otherwise noted.)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
–4–
Test Level
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
CLK
= 18 MHz, decimation factor = 300, 10 pF load on SSI output pins:
1
Min
48
88
100
45
45
2
2
5
5
100
45
45
2
2
3
0.867
38.4
33
–1
–1
VDDH – 0.2
Typ
50%
8
50
10
10
3
VDDH – 0.2
+1
+1
Max
960
1.2
10
10
26
1153
67
0.5
0.2
Unit
f
dB
dB
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
V
V
µA
µA
pF
V
V
CLKOUT
REV. A