AD9874 Analog Devices, AD9874 Datasheet - Page 34

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9874
EXTERNAL PASSIVE COMPONENT REQUIREMENTS
Figure 26 shows an example circuit using the AD9874 and
Table XIV shows the nominal dc bias voltages seen at the differ-
ent pins. The purpose is to show the various external passive
components required by the AD9874, along with nominal dc
voltages for troubleshooting purposes.
Pin Number
1
2
4
5
11
12
13
19
20
35
41
42
43
44
46
47
100pF
50
180pF
Figure 26. Example Circuit Showing Recommended
Component Values
100pF
10nF
100pF
2.2nF
100
pF
Table XIV. Nominal DC Bias Voltages
10
11
12
1
2
3
4
5
6
7
8
9
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
VREFN
100k
Mnemonic
MXOP
MXON
IF2N
IF2P
VREFP
VREFN
RREF
CLKP
CLKN
FREF
CXVM
LON
LOP
CXVL
CXIF
IFIN
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
AD9874
10nF
Nominal DC Bias (V)
VDDI – 0.2
VDDI – 0.2
1.3 – 1.7
1.3 – 1.7
VDDA/2 + 0.250
VDDA/2 – 0.250
1.2
VDDC – 1.3
VDDC – 1.3
VDDC/2
1.6 – 2.0
1.65 – 1.9
1.65 – 1.9
VDDI – 0.05
1.6 – 2.0
0.9 – 1.1
10nF
CLKOUT
SYNCB
DOUTB
DOUTA
GNDS
GNDH
GNDL
VDDH
VDDD
FREF
FS
PE
36
35
34
33
32
30
29
28
27
26
25
31
–34–
The LO, CLK, and IFIN signals are coupled to their respective
inputs using 10 nF capacitors. The output of the mixer is coupled
to the input of the ADC using 100 pF. An external 100 kΩ resistor
from the RREF pin to GND sets up the AD9874’s internal bias
currents. VREFP and VREFN provide a differential reference
voltage to the AD9874’s - ADC and must be decoupled by
a 0.01 µF differential capacitor along with two 100 pF capacitors to
GND. The remaining capacitors are used to decouple other sensi-
tive internal nodes to GND.
Although power supply decoupling capacitors are not shown,
it is recommended that a 0.1 µF surface-mount capacitor be
placed as close as possible to each power supply pin for maxi-
mum effectiveness. Also not shown is the input impedance
matching network used to match the AD9874’s IF input to the
external IF filter. Lastly, the loop filter components associated
with the LO and CLK synthesizers are not shown.
LC component values for f
gram. For other clock frequencies, the two inductors and the
capacitor of the LC tank should be scaled in inverse proportion to
the clock. For example, if f
should be = 6.9 µH and the capacitor should be about 120 pF. A
tolerance of 10% is sufficient for these components since tuning
of the LC tank is performed upon system startup.
APPLICATIONS
Superheterodyne Receiver Example
The AD9874 is well suited for analog and/or digital narrow-
band radio systems based on a superheterodyne receiver
architecture. The superheterodyne architecture is noted for
achieving exceptional dynamic range and selectivity by using
two or more downconversion stages to provide amplification
of the target signal while filtering the undesired signals. The
AD9874 greatly simplifies the design of these radio systems
by integrating the complete IF strip (excluding the LO VCO)
while providing an I/Q digital output (along with other system
parameters) for the demodulation of both analog and digital
modulated signals. The AD9874’s exceptional dynamic range
often simplifies the IF filtering requirements and eliminates the
need for an external AGC.
Figure 27 shows a typical dual conversion superheterodyne
receiver using the AD9874. An RF tuner is used to select and
downconvert the target signal to a suitable first IF for the
AD9874. A preselect filter may precede the tuner to limit the
RF input to the band of interest. The output of the tuner
drives an IF filter that provides partial suppression of adja-
cent channels and interferers that could otherwise limit the
receiver’s dynamic range. The conversion gain of the tuner
should be set such that the peak IF input signal level into the
AD9874 is no greater than –18 dBm to prevent clipping. The
AD9874 downconverts the first IF signal to a second IF that
is exactly 1/8 of the - ADC’s clock rate (i.e., f
plify the digital quadrature demodulation process.
CLK
CLK
= 18 MHz are given on the dia-
= 26 MHz, then the two inductors
CLK
/8) to sim-
REV. A