AD9874 Analog Devices, AD9874 Datasheet - Page 20

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9874
An example may help illustrate how the values of LOA, LOB,
and LOR can be selected. Consider an application employing
a 13 MHz crystal oscillator (i.e., f
requirement that f
high side injection with f
LOR is selected to be 130 such that f
N-divider factor is 1430, which can be realized by selecting
LOB = 178 and LOA = 6.
The stability, phase noise, spur performance, and transient
response of the AD9874’s LO (and CLK) synthesizers are
determined by the external loop filter, the VCO, the N-divide
factor, and the reference frequency, FREF. A good overview
of the theory and practical implementation of PLL synthesiz-
ers (featured as a three-part series in Analog Dialogue) can
be found at:
Also, a free software copy of the Analog Devices ADIsimPLL,
a PLL synthesizer simulation tool, is available at www.analog.com.
Note that the ADF4112 model can be used as a close approxima-
tion to the AD9874’s LO synthesizer when using this software tool.
Figure 6 shows the equivalent input structures of the synthesiz-
ers’ LO and REF buffers (excluding the ESD structures).
The LO input is fed to the LO synthesizer’s buffer as well as
the AD9874’s mixer’s LO port. Both inputs are self-biasing
and thus tolerate ac-coupled inputs. The LO input can be
driven with a single-ended or differential signal. Single-ended
dc-coupled inputs should ensure sufficient signal swing above
and below the common-mode bias of the LO and REF buffers
(i.e., 1.75 V and VDDL/2). Note that the f
dependent and must be driven with input signals exceeding
7.5 V/ s to ensure proper synthesizer operation. If this con-
dition can not be met, an external logic gate can be inserted
prior to the f
f
REF
•
•
•
LOP
LON
input frequency approching dc.
www.analog.com/library/analogDialogue/archives/33-03/
phase/index.html
www.analog.com/library/analogDialogue/archives/33-05/
phase_locked/index.html
www.analog.com/library/analogDialogue/archives/33-07/
phase3/index.html
Figure 6. Equivalent Input of LO and REF Buffers
500
NOTES
1. ESD DIODE STRUCTURES OMITTED FOR CLARITY.
2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON.
REF
input to “square-up” the signal thus allowing a
500
REF
1.75V
BIAS
= 100 kHz and f
BUFFER
IF
LO
= 140.75 MHz and f
TO MIXER
LO PORT
FREF
REF
REF
= 13 MHz) with the
LO
~VDDL/2
REF
= 100 kHz. The
= 143 MHz (i.e.,
input is slew rate
CLK
= 18 MSPS).
84k
–20–
Fast Acquire Mode
The fast acquire circuit attempts to boost the output current
when the phase difference between the divided-down LO
(i.e., f
exceeds the threshold determined by the LOFA register. The
LOFA register specifies a divisor for the f
mines the period (T) of this divided-down clock. This period
defines the time interval used in the fast acquire algorithm to
control the charge pump current.
Assume for the moment that the nominal charge pump current
is at its lowest setting (i.e., LOI = 0) and denote this minimum
current by I
tor exceeds T, the output current for the next pulse is 2I
When the pulse is wider than 2T, the output current for the
next pulse is 3I
output current. If the nominal charge pump current is more
than the minimum value (i.e., LOI > 0), the preceding rule is
only applied if it results in an increase in the instantaneous
charge pump current. If the charge pump current is set to its
lowest value (LOI = 0) and the fast acquire circuit is enabled,
the instantaneous charge pump current will never fall below 2I
when the pulsewidth is less than T. Thus, the charge pump
current when fast acquire is enabled is given by:
The recommended setting for LOFA is LOR/16. Choosing a
larger value for LOFA will increase T. Thus, for a given phase
difference between the LO input and the f
taneous charge pump current will be less than that available for
a LOFA value of LOR/16. Similarly, a smaller value for LOFA
will decrease T, making more current available for the same
phase difference. In other words, a smaller value of LOFA will
enable the synthesizer to settle faster in response to a frequency
hop than will a large LOFA value. Care must be taken to choose
a value for LOFA that is large enough (values greater than 4
recommended) to prevent the loop from oscillating back and
forth in response to a frequency hop.
Address Bit
(Hex)
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Table VII. SPI Registers Associated with LO Synthesizer
I
PUMP FA
LO
) and the divided-down reference frequency (i.e., f
−
Breakdown
(7:0)
(5:0)
(7:0)
(7:5)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(3:0)
(7:0)
0
. When the output pulse from the phase compara-
=
0
, and so forth, up to eight times the minimum
I
0
×
{
1
+
max( ,
Width Value
1
6
8
3
5
8
1
1
3
2
4
8
1
LOI Pulsewidth T
Default
0xFF
0x00
0x38
0x5
0x00
0x1D
0
0
0
0
0x0
0x04
,
REF
REF
input, the instan-
signal that deter-
LOFA(13:8)
LOFA(7:0)
Name
STBY
LOR(13:8)
LOR(7:0)
LOA
LOB(12:8)
LOB(7:0)
LOF
LOINV
LOI
LOTM
)}
REV. A
0
.
REF
(4)
0
)