AD6659 Analog Devices, AD6659 Datasheet - Page 8

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagram
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CH A/CH B DATA
DCOA/DCOB
CLK+
CLK–
VIN
Test Conditions/Comments
SYNC to rising edge of CLK setup time (see Figure 4)
SYNC to rising edge of CLK hold time (see Figure 4)
Setup time between the data and the rising edge of SCLK (see Figure 50)
Hold time between the data and the rising edge of SCLK (see Figure 50)
Period of the SCLK (see Figure 50)
Setup time between CSB and SCLK (see Figure 50)
Hold time between CSB and SCLK (see Figure 50)
SCLK pulse width high (see Figure 50)
SCLK pulse width low (see Figure 50)
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge
SYNC
CLK+
N – 1
t
CH
t
Figure 3. CMOS Interleaved Output Timing
Figure 4. SYNC Input Timing Requirements
SSYNC
t
PD
N
t
CH A
N – 9
t
A
CLK
t
DCO
Rev. | Page 8 of 40
t
SKEW
CH B
N – 9
N + 1
t
HSYNC
N – 8
CH A
CH B
N – 8
N + 2
CH A
N – 7
N + 3
CH B
N – 7
CH A
N – 6
N + 4
CH B
N – 6
CH A
N – 5
Min
2
2
40
2
2
10
10
10
10
N + 5
Typ
0.24
0.40
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns