AD6659 Analog Devices, AD6659 Datasheet - Page 10

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
0, EP
1, 2
3
4 to 7, 25 to 27, 29
8, 9, 11 to 18, 20, 21
10, 19, 28, 37
22
23
24
30 to 36, 38 to 42
43
44
45
46
47
48
Mnemonic
AGND
CLK+, CLK−
SYNC
NC
D0B to D11B
DRVDD
ORB
DCOB
DCOA
D0A to D11A
ORA
SDIO/DCS
SCLK/DFS
CSB
OEB
PDWN
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO
(LSB) D0B
ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
DRVDD
SYNC
CLK+
CLK–
D1B
D2B
D3B
D4B
D5B
D6B
D7B
NC
NC
NC
NC
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Description
Exposed paddle is the only ground connection for the chip. It must be connected to
the printed circuit board (PCB) AGND.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Do Not Connect.
Channel B Digital Outputs. D11B is the MSB and D0B is the LSB.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D11A is the MSB and D0A is the LSB.
Channel A Out-of-Range Digital Output.
SPI Data Input/Output (SDIO). The SDIO function provides bidirectional SPI data I/O in
SPI mode with a 30 kΩ internal pull-down in SPI mode. The duty cycle stabilizer (DCS pin
function) is the static enable input for the duty cycle stabilizer in non-SPI mode with a
30 kΩ internal pull-up in non-SPI (DCS) mode.
SPI Clock (SCLK) Input in SPI Mode/Data Format Select (DFS). 30 kΩ internal pull-down for both
SCLK and DFS. The DFS function provides static control of data output format in non-SPI mode.
When DFS is high, it equals twos complement output. When DFS is low, it equals offset binary
output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
Digital Input. When OEB is low, it enables the Channel A and Channel B digital outputs; when
OEB is high, the outputs are tristated. 30 kΩ internal pull-down.
Digital Input. 30 kΩ internal pull-down. When PDWN is high, it powers down the device.
When PDWN is low, the device runs in normal operation.
PIN 1
INDICATOR
Figure 5. Pin Configuration
Rev. | Page 10 of 40
(Not to Scale)
AD6659
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D11A (MSB)
D10A
D9A
D8A
D7A
DRVDD
D6A
D5A
D4A
D3A