AD6659 Analog Devices, AD6659 Datasheet - Page 7

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
Standby
With NSR Enabled
With QEC Enabled
2
CH A/CH B DATA
1
A
DCOA/DCOB
)
SKEW
CH
CLK+
CLK–
)
)
VIN
PD
DCO
)
)
J
)
CLK
)
N – 1
t
CH
Figure 2. CMOS Output Data Timing
t
PD
N
t
t
A
CLK
t
DCO
Rev. | Page 7 of 40
t
SKEW
N – 9
N + 1
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
N – 8
N + 2
Min
3
12.5
N – 7
N + 3
Typ
6.25
1.0
0.1
3
3
0.1
9
10
11
350
260
2
N – 6
N + 4
Max
480
80
N – 5
N + 5
Unit
MHz
MSPS
ns
ns
ns
ps rms
ns
ns
ns
Cycles
Cycles
Cycles
μs
ns
Cycles
AD6659