AD6659 Analog Devices, AD6659 Datasheet - Page 27

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

DC AND QUADRATURE ERROR CORRECTION (QEC)
In direct conversion or other quadrature systems, mismatches
between the real (I) and imaginary (Q) signal paths cause
frequencies in the positive spectrum to image into the negative
spectrum and vice versa. From an RF point of view, this is
equivalent to information above the LO frequency interfering
with information below the LO frequency, and vice versa. These
mismatches may occur from gain and/or phase mismatches in
the analog quadrature demodulator or in any other mismatches
between the I and Q signal chains. In a single-carrier zero-IF
system where the carrier has been placed symmetrically around
dc, this causes self-distortion of the carrier as the two sidebands
fold onto one another and degrade the EVM of the signal.
In a multicarrier communication system, this mismatch can be
even more problematic because carriers of widely different
power levels can interfere with one another. For example, a large
carrier centered at +f1 can have an image appear at –f1 that is
much larger than the desired carrier at –f1.
The integrated quadrature error correction (QEC) algorithm of
the AD6659 attempts to measure and correct the amplitude and
phase imbalances of the I and Q signal paths to achieve higher
levels of image suppression than is achievable by analog means
alone. These errors can be corrected in an adapted manner,
where the I and Q gain and quadrature phase mismatches are
constantly estimated and corrected, allowing slow changes in
mismatches due to supply and temperature to be constantly
tracked.
The quadrature errors are corrected in a frequency independent
manner on the AD6659; therefore, systems with significant
mismatch in the baseband I and Q signal chains may have
reduced image suppression. The AD6659 QEC still corrects the
systematic imbalances.
The convergence time of the QEC algorithm is dependent on
the statistics of the input signal. For large signals and large
imbalance errors, this convergence time is typically less than
2M samples of the AD6659 data rate.
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LO Leakage (DC) Correction
In a direct conversion receiver subsystem, LO to RF leakage of
the quadrature modulator shows up as dc offsets at baseband.
These offsets are added to dc offsets in the baseband signal
paths and both contribute to a carrier at dc. In a zero-IF receiver,
this dc energy can cause problems because it appears in the
band of a desired channel. As part of the AD6659 QEC
function, the dc offset is suppressed by applying a low
frequency notch filter to form a null around dc. In applications
where constant tracking of the dc offsets and quadrature errors
is not needed, the algorithms can be independently frozen to save
power. When frozen, the image and LO leakage (dc) correction are
still performed, but changes are no longer tracked. Bits[5:3] in
Register 0x110 disable the respective correction when frozen.
The default configuration of the AD6659 has the QEC and dc
correction blocks disabled, and Bits[2:0] in Register 0x110 must
be pulled high to enable the correction blocks. The quadrature
gain, quadrature phase, and dc correction algorithms can also
be disabled independently for system debugging or to save
power by pulling Bits[2:0] low in Register 0x110.
When the QEC is enabled and a correction value has been
calculated, the value remains active as long as any of the QEC
functions (dc, gain, or phase correction) are used.
QEC and DC Correction Range
Table 13 gives the minimum and maximum correction ranges
of the QEC algorithms on the AD6659; if the mismatches are
greater than these ranges, an imperfect correction results.
Table 13. QEC and DC Correction Range
Parameter
Gain
Phase
DC
Minimum
−1.1 dB
−1.79°
−6%
Maximum
+1.0 dB
+1.79°
+6%
AD6659