AD6659 Analog Devices, AD6659 Datasheet - Page 34

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
Addr
(Hex)
0x1A
0x1B
0x1C
0x24
0x2A
0x2E
Digital Feature Control Registers
0x100
0x101
0x110
0x111
0x11D
0x11A
0x112
0x113
0x114
0x116
0x117
0x118
0x119
0x11B
0x11C
0x11E
Register Name
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
BIST signature LSB
Features
Output assign
Sync control
(global)
USR2
QEC Control 0
QEC Control 1
QEC gain band-
width control
QEC phase band-
width control
QEC dc band-
width control
QEC Initial Gain 0
QEC Initial Gain 1
QEC Initial Phase 0
QEC Initial Phase 1
QEC Initial DC I 0
QEC Initial DC I 1
QEC Initial DC Q 0
QEC Initial DC Q 1
NSR Control
Bit 7
(MSB)
B15
B7
B15
Open
Open
Open
Enable
OEB
Pin 47
(local)
Open
Open
Open
Open
Open
Bit 6
B14
B6
B14
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Bit 5
B13
B5
B13
Open
Open
Open
Open
Freeze dc
Open
Open
Initial phase, Bits[7:0]
Initial DC Q, Bits[7:0]
Initial gain, Bits[7:0]
BIST signature [7:0]
Initial DC I, Bits[7:0]
Rev. | Page 34 of 40
Bit 4
B12
B4
B12
Open
Open
Open
Open
Freeze
phase
Open
Initial gain, Bits[14:8]
Initial DC Q, Bits[13:8]
Initial DC I, Bits[13:8]
Bit 3
B11
B3
B11
Open
Open
Open
Enable
GCLK
detect
Freeze
gain
Open
Initial phase, Bits[12:8]
Kexp_phase, Bits[4:0]
Kexp_gain, Bits[4:0]
Kexp_DC, Bits[4:0]
Bit 2
B10
B2
B10
Open
Open
Clock
divider
next
sync
only
Run
GCLK
DC
enable
Force
dc
Noise shaping mode:
1x = band-pass
01 = high pass
00 = low pass
Bit 1
B1
Open
Open
Clock
divider
sync
enable
Open
Phase
enable
Force
phase
B9
B9
Bit 0
(LSB)
B8
B0
B8
OR OE
(local)
0 = ADC A
1 = ADC B
(local)
Master
sync
enable
Disable
SDIO pull-
down
Gain
enable
Force
gain
Enable
NSR
Ch A =
0x02
0x00
0x00
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x01
0x00
Ch B =
0x01
0x01
0x88
0x00
0x00
0x02
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Comments
User-defined
Pattern 1, MSB
User-defined
Pattern 2, LSB
User-defined
Pattern 2, MSB
Least significant
byte of BIST
signature, read
only
Disable the ORx pin
for the indexed
channel
Assigns an ADC to
an output channel
Enables internal
oscillator for clock
rates < 5 MHz