AD6659 Analog Devices, AD6659 Datasheet - Page 3

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

GENERAL DESCRIPTION
The AD6659 is a mixed-signal, dual-channel IF receiver support-
ing radio topologies requiring two receiver signal paths, such as
in main/diversity or direct conversion. This communications
systems processor consists of two high performance analog-to-
digital converters (ADCs) and noise shaping requantizer (NSR)
digital blocks. It is designed to support various communications
applications where high dynamic range performance and small size
are desired.
The high dynamic range ADC core features a multistage differen-
tial pipelined architecture with integrated output error correction
logic. Each ADC features a wide bandwidth switch capacitor
sampling network within the first stage of the differential pipe-
line. An integrated voltage reference eases design considerations.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist region. The
device supports two different output modes selectable via the
serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6659 supports enhanced SNR
performance within a limited region of the Nyquist bandwidth
while maintaining a 12-bit output resolution. The NSR block is
programmed to provide a bandwidth of 20% of the sample
clock. For example, with a sample clock rate of 80 MSPS, the
AD6659 can achieve up to 81.5 dBFS SNR for a 16 MHz
bandwidth at 9.7 MHz AIN.
With the NSR block disabled, the ADC data is provided directly
to the output with an output resolution of 12 bits. The AD6659
can achieve up to 72 dBFS SNR for the entire Nyquist
bandwidth when operated in this mode.
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After digital processing, output data is routed into two 12-bit
output ports that support 1.8 V or 3.3 V CMOS levels.
The AD6659 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the
main and diversity channel. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
The AD6659 also incorporates an optional integrated dc offset
correction and quadrature error correction (QEC) block that
corrects for gain and phase mismatch between the two channels.
This functional block proves invaluable in complex signal
processing applications such as direct conversion receivers.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code, or
twos complement format. A data clock output (DCO) is provided
for each ADC channel to ensure proper latch timing with
receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported,
and output data can be multiplexed onto a single output bus.
The AD6659 is available in a 64-lead, RoHS-compliant LFCSP,
and it is specified over the industrial temperature range
(−40°C to +85°C).
AD6659