SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 653

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SAM3SD8B

Manufacturer Part Number
SAM3SD8B
Description
Manufacturer
Atmel Corporation
Datasheets
Figure 30-7.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
(from master)
(from slave)
TXEMPTY
NPCS0
SPCK
TDRE
MOSI
RDRF
MISO
SPI_TDR
Write in
Status Register Flags Behavior
Figure 30-7
Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg-
ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
Figure 30-8
of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags
behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the
Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data.
The next pointer and counter are not used. The RDRF and TDRE are not shown because these
flags are managed by the PDC when using the PDC.
MSB
1
MSB
shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End
2
6
6
3
5
5
4
4
4
5
3
3
6
6
2
2
7
1
1
shift register empty
SAM3S8/SD8
SAM3S8/SD8
8
LSB
LSB
RDR read
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653

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