SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 560

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

28.7
Figure 28-3. SSC Functional Block Diagram
28.7.1
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560
Functional Description
SAM3S8/SD8
SAM3S8/SD8
Clock Management
APB
MCK
Divider
Interface
Clock
User
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by pro-
gramming the receiver to use the transmit clock and/or to start a data transfer when transmission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro-
grammed to operate with the clock signals provided on either the TK or RK pins. This allows the
SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the master clock divided by 2.
The transmitter clock can be generated by:
• an external clock received on the TK I/O pad
• the receiver clock
• the internal clock divider
Interrupt Control
NVIC
RXEN
TX Start
RF
RC0R
TXEN
RX Start
TF
TX Clock
RK Input
TK Input
RX clock
Selector
Selector
Start
Start
Receive Holding
Transmit Holding
Register
Register
Transmitter
Transmit Clock
Receive Shift Register
TX Start
Receive Clock
Transmit Shift Register
Controller
Controller
Receiver
RX Start
Holding Register
Holding Register
RX Clock
Receive Sync
TX clock
Transmit Sync
Clock Output
Frame Sync
Clock Output
Frame Sync
Controller
Controller
Controller
Controller
Data
Controller
Controller
Data
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
TD
RK
RF
RD
TK
TF