SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 626

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

Figure 29-29. Clock Synchronization in Write Mode
Notes:
626
626
Clock Synchronization in Write Mode
TWI_RHR
TXCOMP
SVREAD
SCLWS
RXRDY
SVACC
TWCK
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
TWD
SAM3S8/SD8
SAM3S8/SD8
SADR.
nism is finished.
S
SADR
As soon as a START is detected
The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or
REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 29-29 on page 626
W
A
DATA0
CLOCK is tied low by the TWI as long as RHR is full
A
describes the clock synchronization in Read mode.
DATA1
DATA0 is not read in the RHR
SCL is stretched on the last bit of DATA1
Rd DATA0
A
Rd DATA1
DATA1
DATA2
NA
Rd DATA2
DATA2
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
S
ADR