AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 920

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.2.2
Register Name:
Access Type:
Offset:
Reset Value:
Note:
• EPnINT: Endpoint n Interrupt
• UPRSM: Upstream Resume Interrupt
• EORSM: End of Resume Interrupt
• WAKEUP: Wakeup Interrupt
• EORST: End of Reset Interrupt
• SOF: Start of Frame Interrupt
32117C–AVR-08/11
EP3INT
31
23
15
7
-
-
-
1. EPnINT bits are within the range from EP0INT to EP6INT.
This bit is cleared when the interrupt source is serviced.
This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is
one.
This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
This bit is set when the USBC sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is
one.
This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.
This bit is set when the USBC detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if
EORSME is one.
This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before) or when the Suspend (SUSP) interrupt bit is set.
This bit is set when the USBC is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This
triggers an interrupt if WAKEUPE is one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.
This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.
This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is
one. The FNUM field is updated.
(1)
Device Global Interrupt Register
EP2INT
UPRSM
30
22
14
6
-
-
UDINT
Read-Only
0x0004
0x00000000
(1)
EP1INT
EORSM
29
21
13
5
-
-
(1)
EP8INT
WAKEUP
EP0INT
28
20
12
4
-
(1)
EP7INT
EORST
27
19
11
3
-
-
(1)
EP6INT
SOF
26
18
10
2
-
-
(1)
EP5INT
25
17
9
1
-
-
-
(1)
AT32UC3C
EP4INT
SUSP
24
16
8
0
-
-
(1)
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