AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 567

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.1
Figure 25-2. Baud Rate Generator
25.6.1.1
32117C–AVR-08/11
Baud Rate Generator
CLK_USART/DIV
CLK
CLK_USART
Baud Rate in Asynchronous Mode
Reserved
USCLKS
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (MR) between:
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (BRGR). If CD is programmed at 0, the Baud Rate Gener-
ator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be longer than a CLK_USART period. The frequency of the signal
provided on CLK must be at least 4.5 times lower than CLK_USART.
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The
resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
0
1
2
3
• Test modes
• CLK_USART
• a division of CLK_USART, the divider being product dependent, but generally set to 8
• the external clock, available on the CLK pin
– Full LIN error checking and reporting
– Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
– Generation of the Wakeup signal
– Remote loopback, local loopback, automatic echo
16-bit Counter
CD
USCLKS= 3
0
SYNC
CD
>1
0
1
0
1
OVER
Sampling
Divider
FIDI
0
1
SYNC
AT32UC3C
CLK
BaudRate
Sampling
Clock
Clock
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